From patchwork Wed May 27 03:20:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 6486961 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 85D87C0020 for ; Wed, 27 May 2015 03:21:38 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3572C20703 for ; Wed, 27 May 2015 03:21:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 1EF2520700 for ; Wed, 27 May 2015 03:21:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B80566E8F8; Tue, 26 May 2015 20:21:19 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qk0-f170.google.com (mail-qk0-f170.google.com [209.85.220.170]) by gabe.freedesktop.org (Postfix) with ESMTP id A02B16E8E5 for ; Tue, 26 May 2015 20:21:05 -0700 (PDT) Received: by qkdn188 with SMTP id n188so105310414qkd.2 for ; Tue, 26 May 2015 20:21:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; bh=E5d8zjMTNAhh21cydtJTaqgaA9Pl32SroMYCRrSjjk8=; b=w8Qq2KmaeNlaNmTPH8t10hRtPK0E1ALHS4EWlIkeCTkenIFhO5A6mw/BsPCgs7iTAG juJ9RR6QnkDKpPuLOJpbzEH54uaHJ59j72fsnj9890113CdMx+qv+txq6OOfsoloc+77 KSUkdxpzPUixBAqG+BQJC7w7/WpCukJN19H9FUoHX/19f+m2IVuPwaEbyo2Rce6JPZ0K oEZvwgNWlemWETyEm2uCVPI9/nhdwLtHa1sIUcPKpMkcWbvfm8SS+YNCDIlAGvLT8Cgk yzdKIPhC1FfufS3q4V9/vycRrP1+4dZGE0E1/n2JJ8pP/U7xnDsFEdQbOc74aFrIfvZy gkJQ== X-Received: by 10.55.54.136 with SMTP id d130mr60626751qka.22.1432696865353; Tue, 26 May 2015 20:21:05 -0700 (PDT) Received: from localhost.localdomain (static-74-96-105-49.washdc.fios.verizon.net. [74.96.105.49]) by mx.google.com with ESMTPSA id 20sm9629127qhf.14.2015.05.26.20.21.04 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 May 2015 20:21:05 -0700 (PDT) From: Alex Deucher X-Google-Original-From: Alex Deucher To: dri-devel@lists.freedesktop.org Subject: [PATCH 81/88] drm/amdgpu: recalculate VCE firmware BO size Date: Tue, 26 May 2015 23:20:20 -0400 Message-Id: <1432696827-3752-51-git-send-email-alexander.deucher@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1432696827-3752-1-git-send-email-alexander.deucher@amd.com> References: <1432696827-3752-1-git-send-email-alexander.deucher@amd.com> MIME-Version: 1.0 Cc: Leo Liu X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Leo Liu Firmware required BO size changes in terms of ASIC family Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 5 +---- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 2 +- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 13 +++++++++---- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 13 +++++++++---- 5 files changed, 20 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index ebff89e..52d6845 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1664,8 +1664,6 @@ struct amdgpu_uvd { * VCE */ #define AMDGPU_MAX_VCE_HANDLES 16 -#define AMDGPU_VCE_STACK_SIZE (1024*1024) -#define AMDGPU_VCE_HEAP_SIZE (4*1024*1024) #define AMDGPU_VCE_FIRMWARE_OFFSET 256 struct amdgpu_vce { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 803ee60..62018b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -68,9 +68,8 @@ static void amdgpu_vce_idle_work_handler(struct work_struct *work); * * First step to get VCE online, allocate memory and load the firmware */ -int amdgpu_vce_sw_init(struct amdgpu_device *adev) +int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) { - unsigned long size; const char *fw_name; const struct common_firmware_header *hdr; unsigned ucode_version, version_major, version_minor, binary_id; @@ -136,8 +135,6 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev) /* allocate firmware, stack and heap BO */ - size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes)) + - AMDGPU_VCE_STACK_SIZE + AMDGPU_VCE_HEAP_SIZE; r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM, 0, NULL, &adev->vce.vcpu_bo); if (r) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h index b9411e4..4294854 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h @@ -24,7 +24,7 @@ #ifndef __AMDGPU_VCE_H__ #define __AMDGPU_VCE_H__ -int amdgpu_vce_sw_init(struct amdgpu_device *adev); +int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size); int amdgpu_vce_sw_fini(struct amdgpu_device *adev); int amdgpu_vce_suspend(struct amdgpu_device *adev); int amdgpu_vce_resume(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index b47c16d..f200df3 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -37,6 +37,10 @@ #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h" +#define VCE_V2_0_FW_SIZE (256 * 1024) +#define VCE_V2_0_STACK_SIZE (64 * 1024) +#define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES) + static void vce_v2_0_mc_resume(struct amdgpu_device *adev); static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev); @@ -183,7 +187,8 @@ static int vce_v2_0_sw_init(struct amdgpu_device *adev) if (r) return r; - r = amdgpu_vce_sw_init(adev); + r = amdgpu_vce_sw_init(adev, VCE_V2_0_FW_SIZE + + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE); if (r) return r; @@ -415,17 +420,17 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev) WREG32(mmVCE_LMI_VM_CTRL, 0); addr += AMDGPU_VCE_FIRMWARE_OFFSET; - size = AMDGPU_GPU_PAGE_ALIGN(adev->vce.fw->size); + size = VCE_V2_0_FW_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE0, size); addr += size; - size = AMDGPU_VCE_STACK_SIZE; + size = VCE_V2_0_STACK_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE1, size); addr += size; - size = AMDGPU_VCE_HEAP_SIZE; + size = VCE_V2_0_DATA_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE2, size); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 384c45e..ee29436f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -35,6 +35,10 @@ #include "oss/oss_2_0_d.h" #include "oss/oss_2_0_sh_mask.h" +#define VCE_V3_0_FW_SIZE (384 * 1024) +#define VCE_V3_0_STACK_SIZE (64 * 1024) +#define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024)) + static void vce_v3_0_mc_resume(struct amdgpu_device *adev); static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev); @@ -181,7 +185,8 @@ static int vce_v3_0_sw_init(struct amdgpu_device *adev) if (r) return r; - r = amdgpu_vce_sw_init(adev); + r = amdgpu_vce_sw_init(adev, VCE_V3_0_FW_SIZE + + (VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE) * 2); if (r) return r; @@ -304,17 +309,17 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev) WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8)); offset = AMDGPU_VCE_FIRMWARE_OFFSET; - size = AMDGPU_GPU_PAGE_ALIGN(adev->vce.fw->size); + size = VCE_V3_0_FW_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE0, size); offset += size; - size = AMDGPU_VCE_STACK_SIZE; + size = VCE_V3_0_STACK_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE1, size); offset += size; - size = AMDGPU_VCE_HEAP_SIZE; + size = VCE_V3_0_DATA_SIZE; WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff); WREG32(mmVCE_VCPU_CACHE_SIZE2, size);