From patchwork Fri Jun 5 08:33:46 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Abriou X-Patchwork-Id: 6552171 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1B8D0C0020 for ; Fri, 5 Jun 2015 09:01:16 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 38CC5207A0 for ; Fri, 5 Jun 2015 09:01:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 2809C20792 for ; Fri, 5 Jun 2015 09:01:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5439D6E490; Fri, 5 Jun 2015 02:01:11 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by gabe.freedesktop.org (Postfix) with ESMTP id EC4126E495 for ; Fri, 5 Jun 2015 02:01:09 -0700 (PDT) Received: from pps.filterd (m0046670.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.14.5/8.14.5) with SMTP id t558MfNA032650; Fri, 5 Jun 2015 10:33:53 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 1ut4es15wv-1 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 05 Jun 2015 10:33:53 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D3B703F; Fri, 5 Jun 2015 08:33:51 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C11DB2AED; Fri, 5 Jun 2015 08:33:51 +0000 (GMT) Received: from localhost (10.201.23.35) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.195.1; Fri, 5 Jun 2015 10:33:51 +0200 From: Vincent Abriou To: Subject: [PATCH 2/2] drm/sti: vtg fix CEA-861E video format timing error Date: Fri, 5 Jun 2015 10:33:46 +0200 Message-ID: <1433493226-22971-3-git-send-email-vincent.abriou@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1433493226-22971-1-git-send-email-vincent.abriou@st.com> References: <1433493226-22971-1-git-send-email-vincent.abriou@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.35] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.14.151, 1.0.33, 0.0.0000 definitions=2015-06-05_07:2015-06-05, 2015-06-05, 1970-01-01 signatures=0 Cc: Fabien Dessenne , Benjamin Gaignard , kernel@stlinux.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP HDMI analyzer tests showed that Vsync and Hsync signal were not compliant with the HDMI protocol. HDMI_DELAY should be taken into account in the VTG Vsync programming to reflect the 6 pixels shift introduced in the VTG Hsync programming. Signed-off-by: Vincent Abriou --- drivers/gpu/drm/sti/sti_vtg.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/sti/sti_vtg.c b/drivers/gpu/drm/sti/sti_vtg.c index eda62c8..d21df0d 100644 --- a/drivers/gpu/drm/sti/sti_vtg.c +++ b/drivers/gpu/drm/sti/sti_vtg.c @@ -151,8 +151,11 @@ static void vtg_set_mode(struct sti_vtg *vtg, tmp |= 1; writel(tmp, vtg->regs + VTG_TOP_V_VD_1); writel(tmp, vtg->regs + VTG_BOT_V_VD_1); - writel(0, vtg->regs + VTG_TOP_V_HD_1); - writel(0, vtg->regs + VTG_BOT_V_HD_1); + + tmp = HDMI_DELAY << 16; + tmp |= HDMI_DELAY; + writel(tmp, vtg->regs + VTG_TOP_V_HD_1); + writel(tmp, vtg->regs + VTG_BOT_V_HD_1); /* prepare VTG set 2 for for HD DCS */ tmp = (mode->hsync_end - mode->hsync_start) << 16;