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Fri, 12 Jun 2015 05:59:29 -0700 (PDT) Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NPU00TVT1F4JM00@mailout2.samsung.com> for dri-devel@lists.freedesktop.org; Fri, 12 Jun 2015 21:59:28 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.115]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 11.9A.28411.0B7DA755; Fri, 12 Jun 2015 21:59:28 +0900 (KST) X-AuditID: cbfee68e-f79c56d000006efb-e7-557ad7b01087 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 9C.25.25346.FA7DA755; Fri, 12 Jun 2015 21:59:28 +0900 (KST) Received: from localhost.localdomain ([10.252.82.145]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NPU002KS1F1AP00@mmp2.samsung.com>; Fri, 12 Jun 2015 21:59:27 +0900 (KST) From: Hyungwon Hwang To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: [PATCH v6 08/15] drm/exynos: dsi: rename pll_clk to sclk_clk Date: Fri, 12 Jun 2015 21:59:03 +0900 Message-id: <1434113958-15877-9-git-send-email-human.hwang@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1434113958-15877-1-git-send-email-human.hwang@samsung.com> References: <1434113958-15877-1-git-send-email-human.hwang@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOLMWRmVeSWpSXmKPExsWyRsSkWHfD9apQg9kPuSyutE5ntZh/5Byr xZWv79ksls7oY7WYdH8Ci8WLexdZLGZMfsnmwO7x4us2Zo/73ceZPPq2rGL0+LxJLoAlissm JTUnsyy1SN8ugSvj+rO9bAWH1Ssuz25nbGC8ptDFyMkhIWAi0duwkhXCFpO4cG89WxcjF4eQ wFJGiXWXfjPBFM14tw0qMZ1RYtGDD0wQzg8g5/s+sCo2AT2JBdd+sIPYIgL2Eou/nmIFKWIW 6GaUWHn+KVCCg0NYwFVi4REVkBoWAVWJPa93sYDYvALuEvuPf2SE2CYncfLYZLCTOAU8JO4e vAVWIwRU8//+IXaQmRIC/ewSl2c9YIEYJCDxbfIhFpD5EgKyEpsOMEPMkZQ4uOIGywRG4QWM DKsYRVMLkguKk9KLjPSKE3OLS/PS9ZLzczcxAsP79L9nfTsYbx6wPsQowMGoxMOboFUVKsSa WFZcmXuI0RRow0RmKdHkfGAU5ZXEGxqbGVmYmpgaG5lbmimJ8yZI/QwWEkhPLEnNTk0tSC2K LyrNSS0+xMjEwSnVwGjtxPOC6Swvu2PJjtrDdfv/dG672WVuwLtN8MmDvidfCsvvPDjBfiXd RPjGqYkR672n3ffUSOvaf2P2OzsJJpb1S+S2TQ70Ld+3vzFk3v3Lf75PsbPlXvtGeMvL676h YZu02FK6nHklkq5tnmJ960G4Imd5vtJjlfWcob88NrKLb1t4cGXjtrVKLMUZiYZazEXFiQAE hI1IagIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrIIsWRmVeSWpSXmKPExsVy+t9jQd0N16tCDd5vYrW40jqd1WL+kXNA 1tf3bBZLZ/SxWky6P4HF4sW9iywWMya/ZHNg93jxdRuzx/3u40wefVtWMXp83iQXwBLVwGiT kZqYklqkkJqXnJ+SmZduq+QdHO8cb2pmYKhraGlhrqSQl5ibaqvk4hOg65aZA3SCkkJZYk4p UCggsbhYSd8O04TQEDddC5jGCF3fkCC4HiMDNJCwhjHj+rO9bAWH1Ssuz25nbGC8ptDFyMkh IWAiMePdNjYIW0ziwr31QDYXh5DAdEaJRQ8+MEE4P4Cc7/uYQKrYBPQkFlz7wQ5iiwjYSyz+ eooVpIhZoJtRYuX5p0AJDg5hAVeJhUdUQGpYBFQl9rzexQJi8wq4S+w//pERYpucxMljk1lB bE4BD4m7B2+B1QgB1fy/f4h9AiPvAkaGVYyiqQXJBcVJ6bmGesWJucWleel6yfm5mxjB0fNM agfjygaLQ4wCHIxKPLwP/atChVgTy4orcw8xSnAwK4nwdm8HCvGmJFZWpRblxxeV5qQWH2I0 BbpqIrOUaHI+MLLzSuINjU3MjCyNzA0tjIzNlcR5T+b7hAoJpCeWpGanphakFsH0MXFwSjUw +telzPO4M+vr34jZV7Jnlf6/tObC9R7DiHvTfV89r39r+PdC7cSS30LNn5vjyxn7NDZZJcsx yFVqVhS8dj0js/7Y9ID1ylb5FY5/psxamlX0jSdT69GuzUVcU91PMO1cl8G2ZnPNPoYzt+vE V+/a7TJV/biKqfHTVyUa+zWlPBL2P2kp1SsRVGIpzkg01GIuKk4EAK/Sc9a0AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: sw0312.kim@samsung.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk is actually not the pll input clock for dsi. The pll input clock comes from the board's oscillator directly. But for the backward compatibility, the old clock name "pll_clk" is also OK. Signed-off-by: Hyungwon Hwang --- Changes before: - Refer https://patchwork.kernel.org/patch/6191721 Changes for v6: - Merged 2 patches drm/exynos: dsi: add the backward compatibility for the renamed clock drm/exynos: dsi: rename pll_clk to sclk_clk .../devicetree/bindings/video/exynos_dsim.txt | 7 +++-- drivers/gpu/drm/exynos/exynos_drm_dsi.c | 36 ++++++++++------------ 2 files changed, 20 insertions(+), 23 deletions(-) -- 1.9.1 diff --git a/Documentation/devicetree/bindings/video/exynos_dsim.txt b/Documentation/devicetree/bindings/video/exynos_dsim.txt index 802aa7e..44659dd 100644 --- a/Documentation/devicetree/bindings/video/exynos_dsim.txt +++ b/Documentation/devicetree/bindings/video/exynos_dsim.txt @@ -10,13 +10,14 @@ Required properties: - interrupts: should contain DSI interrupt - clocks: list of clock specifiers, must contain an entry for each required entry in clock-names - - clock-names: should include "bus_clk"and "pll_clk" entries + - clock-names: should include "bus_clk"and "sclk_mipi" entries + the use of "pll_clk" is deprecated - phys: list of phy specifiers, must contain an entry for each required entry in phy-names - phy-names: should include "dsim" entry - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V) - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V) - - samsung,pll-clock-frequency: specifies frequency of the "pll_clk" clock + - samsung,pll-clock-frequency: specifies frequency of the oscillator clock - #address-cells, #size-cells: should be set respectively to <1> and <0> according to DSI host bindings (see MIPI DSI bindings [1]) @@ -48,7 +49,7 @@ Example: reg = <0x11C80000 0x10000>; interrupts = <0 79 0>; clocks = <&clock 286>, <&clock 143>; - clock-names = "bus_clk", "pll_clk"; + clock-names = "bus_clk", "sclk_mipi"; phys = <&mipi_phy 1>; phy-names = "dsim"; vddcore-supply = <&vusb_reg>; diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index c1999ad..a3bfac2 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -235,6 +235,8 @@ #define DSI_XFER_TIMEOUT_MS 100 #define DSI_RX_FIFO_EMPTY 0x30800002 +#define OLD_SCLK_MIPI_CLK_NAME "pll_clk" + enum exynos_dsi_transfer_type { EXYNOS_DSI_TX, EXYNOS_DSI_RX, @@ -279,7 +281,7 @@ struct exynos_dsi { void __iomem *reg_base; struct phy *phy; - struct clk *pll_clk; + struct clk *sclk_clk; struct clk *bus_clk; struct regulator_bulk_data supplies[2]; int irq; @@ -433,16 +435,7 @@ static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi, u16 m; u32 reg; - clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate); - - fin = clk_get_rate(dsi->pll_clk); - if (!fin) { - dev_err(dsi->dev, "failed to get PLL clock frequency\n"); - return 0; - } - - dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin); - + fin = dsi->pll_clk_rate; fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s); if (!fout) { dev_err(dsi->dev, @@ -1313,10 +1306,10 @@ static int exynos_dsi_poweron(struct exynos_dsi *dsi) goto err_bus_clk; } - ret = clk_prepare_enable(dsi->pll_clk); + ret = clk_prepare_enable(dsi->sclk_clk); if (ret < 0) { dev_err(dsi->dev, "cannot enable pll clock %d\n", ret); - goto err_pll_clk; + goto err_sclk_clk; } ret = phy_power_on(dsi->phy); @@ -1328,8 +1321,8 @@ static int exynos_dsi_poweron(struct exynos_dsi *dsi) return 0; err_phy: - clk_disable_unprepare(dsi->pll_clk); -err_pll_clk: + clk_disable_unprepare(dsi->sclk_clk); +err_sclk_clk: clk_disable_unprepare(dsi->bus_clk); err_bus_clk: regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); @@ -1355,7 +1348,7 @@ static void exynos_dsi_poweroff(struct exynos_dsi *dsi) phy_power_off(dsi->phy); - clk_disable_unprepare(dsi->pll_clk); + clk_disable_unprepare(dsi->sclk_clk); clk_disable_unprepare(dsi->bus_clk); ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); @@ -1722,10 +1715,13 @@ static int exynos_dsi_probe(struct platform_device *pdev) return -EPROBE_DEFER; } - dsi->pll_clk = devm_clk_get(dev, "pll_clk"); - if (IS_ERR(dsi->pll_clk)) { - dev_info(dev, "failed to get dsi pll input clock\n"); - return PTR_ERR(dsi->pll_clk); + dsi->sclk_clk = devm_clk_get(dev, "sclk_mipi"); + if (IS_ERR(dsi->sclk_clk)) { + dsi->sclk_clk = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME); + if (IS_ERR(dsi->sclk_clk)) { + dev_info(dev, "failed to get dsi sclk clock\n"); + eturn PTR_ERR(dsi->sclk_clk); + } } dsi->bus_clk = devm_clk_get(dev, "bus_clk");