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[74.96.105.49]) by smtp.gmail.com with ESMTPSA id 78sm1719989qhv.38.2015.07.08.10.46.10 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Jul 2015 10:46:10 -0700 (PDT) From: Alex Deucher X-Google-Original-From: Alex Deucher To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/3] drm/radeon/evergreen: only enable CP gui idle interrupts after CP is set up Date: Wed, 8 Jul 2015 13:46:03 -0400 Message-Id: <1436377564-24111-2-git-send-email-alexander.deucher@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1436377564-24111-1-git-send-email-alexander.deucher@amd.com> References: <1436377564-24111-1-git-send-email-alexander.deucher@amd.com> Cc: Alex Deucher , stable@vger.kernel.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Necessary for proper gfx/rlc/smu handshaking. Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org --- drivers/gpu/drm/radeon/evergreen.c | 12 ++++++++++-- drivers/gpu/drm/radeon/r600.c | 4 ++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 0acde19..0e0fb07 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -216,6 +216,8 @@ extern void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer); extern u32 cik_get_csb_size(struct radeon_device *rdev); extern void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer); extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev); +extern void r600_enable_gui_idle_interrupt(struct radeon_device *rdev, + bool enable); static const u32 evergreen_golden_registers[] = { @@ -3037,6 +3039,8 @@ static int evergreen_cp_resume(struct radeon_device *rdev) WREG32(GRBM_SOFT_RESET, 0); RREG32(GRBM_SOFT_RESET); + r600_enable_gui_idle_interrupt(rdev, false); + /* Set ring buffer size */ rb_bufsz = order_base_2(ring->ring_size / 8); tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; @@ -3082,6 +3086,9 @@ static int evergreen_cp_resume(struct radeon_device *rdev) ring->ready = false; return r; } + + r600_enable_gui_idle_interrupt(rdev, true); + return 0; } @@ -4419,7 +4426,7 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev) tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; WREG32(CAYMAN_DMA1_CNTL, tmp); } else - WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); + WREG32(CP_INT_CNTL, 0); tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; WREG32(DMA_CNTL, tmp); WREG32(GRBM_INT_CNTL, 0); @@ -4468,7 +4475,7 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev) int evergreen_irq_set(struct radeon_device *rdev) { - u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; + u32 cp_int_cntl = 0; u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0; u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; @@ -4526,6 +4533,7 @@ int evergreen_irq_set(struct radeon_device *rdev) cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; } } else { + cp_int_cntl = RREG32(CP_INT_CNTL) & ~(RB_INT_ENABLE | TIME_STAMP_INT_ENABLE); if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { DRM_DEBUG("evergreen_irq_set: sw int gfx\n"); cp_int_cntl |= RB_INT_ENABLE; diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 0bc39cd..df59d8c 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -2710,8 +2710,8 @@ int r600_cp_start(struct radeon_device *rdev) return 0; } -static void r600_enable_gui_idle_interrupt(struct radeon_device *rdev, - bool enable) +void r600_enable_gui_idle_interrupt(struct radeon_device *rdev, + bool enable) { u32 tmp = RREG32(CP_INT_CNTL);