From patchwork Fri Jul 17 08:26:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Pinchart X-Patchwork-Id: 6813791 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id A4CA79F6CE for ; Fri, 17 Jul 2015 08:25:55 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C6A0720672 for ; Fri, 17 Jul 2015 08:25:54 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id ED49420674 for ; Fri, 17 Jul 2015 08:25:53 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DD3A16E78E; Fri, 17 Jul 2015 01:25:52 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from galahad.ideasonboard.com (galahad.ideasonboard.com [185.26.127.97]) by gabe.freedesktop.org (Postfix) with ESMTPS id 82D866E79F for ; Fri, 17 Jul 2015 01:25:48 -0700 (PDT) Received: from avalon.pp.htv.fi (89-27-67-84.bb.dnainternet.fi [89.27.67.84]) by galahad.ideasonboard.com (Postfix) with ESMTPSA id C443921694; Fri, 17 Jul 2015 10:25:07 +0200 (CEST) From: Laurent Pinchart To: linux-sh@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH 3/5] ARM: shmobile: r8a7794: Add DU0 clock Date: Fri, 17 Jul 2015 11:26:05 +0300 Message-Id: <1437121567-18467-4-git-send-email-laurent.pinchart+renesas@ideasonboard.com> X-Mailer: git-send-email 2.3.6 In-Reply-To: <1437121567-18467-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com> References: <1437121567-18467-1-git-send-email-laurent.pinchart+renesas@ideasonboard.com> Cc: Magnus Damm X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The DU0 clock is an MSTP clock, child of the CPG ZX clock. Signed-off-by: Laurent Pinchart Acked-by: by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7794.dtsi | 7 ++++--- include/dt-bindings/clock/r8a7794-clock.h | 1 + 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index b73819423311..2a0d375e45b3 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -675,19 +675,20 @@ reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; + <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&zx_clk>; #clock-cells = <1>; clock-indices = < R8A7794_CLK_EHCI R8A7794_CLK_HSUSB R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 - R8A7794_CLK_SCIF0 + R8A7794_CLK_SCIF0 R8A7794_CLK_DU0 >; clock-output-names = "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", - "scif3", "scif2", "scif1", "scif0"; + "scif3", "scif2", "scif1", "scif0", "du0"; }; mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index 09da38a58776..a7a7e0370968 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -79,6 +79,7 @@ #define R8A7794_CLK_SCIF2 19 #define R8A7794_CLK_SCIF1 20 #define R8A7794_CLK_SCIF0 21 +#define R8A7794_CLK_DU0 24 /* MSTP8 */ #define R8A7794_CLK_VIN1 10