From patchwork Fri Jul 31 22:22:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 6920741 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5A4CCC05AC for ; Fri, 31 Jul 2015 22:23:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8CDE520653 for ; Fri, 31 Jul 2015 22:23:07 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 24BE320687 for ; Fri, 31 Jul 2015 22:23:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 24C386EDFA; Fri, 31 Jul 2015 15:23:03 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-yk0-f180.google.com (mail-yk0-f180.google.com [209.85.160.180]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2B2EA6EDF0 for ; Fri, 31 Jul 2015 15:23:00 -0700 (PDT) Received: by ykay190 with SMTP id y190so70352225yka.3 for ; Fri, 31 Jul 2015 15:22:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nrTO/UPIxGb+Ox1X14UcsD9B7na4KP4LfprS87wnFs8=; b=yvsHAXUtLvHrzbp3BNJLltfiBOwGcdqDIIu2yWcUjNycG8ep5yqpPfiu/mSFlCerKQ YHhFKXme96zGjxUxBAbKNRsMdTP+/S6IFtzQvVYMAL79R1Bf2c/nsAjOHV1sD4+HyMmg KCO9+z7tDlKe7H5JSENS0pjEPn9pzyoKGfpBVct+n1JtFilSqNC4SfJX+duyds5EnDX0 Rs41Z+rh+VQuv3FJHoY036yzn2VPpeD0p7jdasiJfbXjbL5zO+ugcKwhPSPuEZSgWBdu 0aVfDp34dA25IKBy5fmmOa6lLdXWjAS3XkMko87gJKWkCu+mzr8Pa/hgD2EsOwzwfken 8FUA== X-Received: by 10.170.94.84 with SMTP id l81mr6358697yka.93.1438381379568; Fri, 31 Jul 2015 15:22:59 -0700 (PDT) Received: from localhost.localdomain (static-74-96-105-49.washdc.fios.verizon.net. [74.96.105.49]) by smtp.gmail.com with ESMTPSA id u78sm5438990ywu.13.2015.07.31.15.22.58 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 31 Jul 2015 15:22:59 -0700 (PDT) From: Alex Deucher X-Google-Original-From: Alex Deucher To: dri-devel@lists.freedesktop.org Subject: [PATCH 08/31] drm/amdgpu: use scheduler user seq instead of previous user seq Date: Fri, 31 Jul 2015 18:22:24 -0400 Message-Id: <1438381367-24980-9-git-send-email-alexander.deucher@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1438381367-24980-1-git-send-email-alexander.deucher@amd.com> References: <1438381367-24980-1-git-send-email-alexander.deucher@amd.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Chunming Zhou Signed-off-by: Chunming Zhou Acked-by: Christian K?nig Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index 557fb60..b9be250 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -225,10 +225,16 @@ uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, struct fence *fence) { struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; - uint64_t seq = cring->sequence; - unsigned idx = seq % AMDGPU_CTX_MAX_CS_PENDING; - struct fence *other = cring->fences[idx]; + uint64_t seq = 0; + unsigned idx = 0; + struct fence *other = NULL; + if (amdgpu_enable_scheduler) + seq = atomic64_read(&cring->c_entity.last_queued_v_seq); + else + seq = cring->sequence; + idx = seq % AMDGPU_CTX_MAX_CS_PENDING; + other = cring->fences[idx]; if (other) { signed long r; r = fence_wait_timeout(other, false, MAX_SCHEDULE_TIMEOUT); @@ -240,7 +246,8 @@ uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, spin_lock(&ctx->ring_lock); cring->fences[idx] = fence; - cring->sequence++; + if (!amdgpu_enable_scheduler) + cring->sequence++; spin_unlock(&ctx->ring_lock); fence_put(other); @@ -253,14 +260,21 @@ struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, { struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx]; struct fence *fence; + uint64_t queued_seq; spin_lock(&ctx->ring_lock); - if (seq >= cring->sequence) { + if (amdgpu_enable_scheduler) + queued_seq = atomic64_read(&cring->c_entity.last_queued_v_seq) + 1; + else + queued_seq = cring->sequence; + + if (seq >= queued_seq) { spin_unlock(&ctx->ring_lock); return ERR_PTR(-EINVAL); } - if (seq + AMDGPU_CTX_MAX_CS_PENDING < cring->sequence) { + + if (seq + AMDGPU_CTX_MAX_CS_PENDING < queued_seq) { spin_unlock(&ctx->ring_lock); return NULL; }