From patchwork Wed Aug 19 14:50:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yakir Yang X-Patchwork-Id: 7040331 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7D9399F372 for ; Thu, 20 Aug 2015 02:09:27 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 94EE6207D9 for ; Thu, 20 Aug 2015 02:09:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 22FFE207C0 for ; Thu, 20 Aug 2015 02:09:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2B5AF7215F; Wed, 19 Aug 2015 19:09:00 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id 075296E745 for ; Wed, 19 Aug 2015 07:50:34 -0700 (PDT) Received: from ykk?rock-chips.com (unknown [192.168.167.131]) by regular1.263xmail.com (Postfix) with SMTP id 4540B4F08; Wed, 19 Aug 2015 22:50:28 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 17664422; Wed, 19 Aug 2015 22:50:22 +0800 (CST) X-RL-SENDER: ykk@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: ykk@rock-chips.com X-UNIQUE-TAG: <1b820075553a2a23b1c7b2fb70c79348> X-ATTACHMENT-NUM: 0 X-SENDER: ykk@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 26165LS0RTA; Wed, 19 Aug 2015 22:50:25 +0800 (CST) From: Yakir Yang To: Heiko Stuebner , Thierry Reding , Jingoo Han , Fabio Estevam , Inki Dae , joe@perches.com, Russell King Subject: [PATCH v3 05/14] drm: bridge/analogix_dp: fix link_rate & lane_count bug Date: Wed, 19 Aug 2015 09:50:24 -0500 Message-Id: <1439995824-18312-1-git-send-email-ykk@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1439995728-18046-1-git-send-email-ykk@rock-chips.com> References: <1439995728-18046-1-git-send-email-ykk@rock-chips.com> X-Mailman-Approved-At: Wed, 19 Aug 2015 19:08:55 -0700 Cc: seanpaul@google.com, dri-devel@lists.freedesktop.org, Andrzej Hajda , Yakir Yang , Gustavo Padovan , linux-samsung-soc@vger.kernel.org, Vincent Palatin , linux-rockchip@lists.infradead.org, Kishon Vijay Abraham I , devicetree@vger.kernel.org, Pawel Moll , Ian Campbell , dianders@google.com, Rob Herring , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kyungmin Park , djkurtz@google.com, Kumar Gala , ajaynumb@gmail.com, Andy Yan X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP link_rate and lane_count already configed in analogix_dp_set_link_train(), so we don't need to config those repeatly after training finished, just remove them out. Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}. Signed-off-by: Yakir Yang --- Changes in v3: - Take Thierry Reding suggest, link_rate and lane_count shouldn't config to the DT property value directly, but we can take those as hardware limite. For example, RK3288 only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would like "link-rate = 0x0a" "lane-count = 4". Changes in v2: None drivers/gpu/drm/bridge/analogix_dp_core.c | 16 ++++++++-------- drivers/gpu/drm/bridge/analogix_dp_core.h | 9 +++++---- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/bridge/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix_dp_core.c index 480cc13..1778e0a 100644 --- a/drivers/gpu/drm/bridge/analogix_dp_core.c +++ b/drivers/gpu/drm/bridge/analogix_dp_core.c @@ -635,6 +635,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp, /* * For DP rev.1.1, Maximum link rate of Main Link lanes * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps + * For DP rev.1.2, Maximum link rate of Main Link lanes + * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps */ analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); *bandwidth = data; @@ -668,7 +670,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp, analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && - (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { + (dp->link_train.link_rate != LINK_RATE_2_70GBPS) && + (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) { dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", dp->link_train.link_rate); dp->link_train.link_rate = LINK_RATE_1_62GBPS; @@ -901,8 +904,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp) return; } - ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count, - dp->video_info->link_rate); + ret = analogix_dp_set_link_train(dp, dp->video_info->max_lane_count, + dp->video_info->max_link_rate); if (ret) { dev_err(dp->dev, "unable to do link train\n"); return; @@ -912,9 +915,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp) analogix_dp_enable_rx_to_enhanced_mode(dp, 1); analogix_dp_enable_enhanced_mode(dp, 1); - analogix_dp_set_lane_count(dp, dp->video_info->lane_count); - analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate); - analogix_dp_init_video(dp); ret = analogix_dp_config_video(dp); if (ret) @@ -1198,13 +1198,13 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev) } if (of_property_read_u32(dp_node, "analogix,link-rate", - &dp_video_config->link_rate)) { + &dp_video_config->max_link_rate)) { dev_err(dev, "failed to get link-rate\n"); return ERR_PTR(-EINVAL); } if (of_property_read_u32(dp_node, "analogix,lane-count", - &dp_video_config->lane_count)) { + &dp_video_config->max_lane_count)) { dev_err(dev, "failed to get lane-count\n"); return ERR_PTR(-EINVAL); } diff --git a/drivers/gpu/drm/bridge/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix_dp_core.h index 2cefde9..941b34f 100644 --- a/drivers/gpu/drm/bridge/analogix_dp_core.h +++ b/drivers/gpu/drm/bridge/analogix_dp_core.h @@ -21,8 +21,9 @@ #define MAX_EQ_LOOP 5 enum link_rate_type { - LINK_RATE_1_62GBPS = 0x06, - LINK_RATE_2_70GBPS = 0x0a + LINK_RATE_1_62GBPS = DP_LINK_BW_1_62, + LINK_RATE_2_70GBPS = DP_LINK_BW_2_7, + LINK_RATE_5_40GBPS = DP_LINK_BW_5_4, }; enum link_lane_count_type { @@ -128,8 +129,8 @@ struct video_info { enum color_coefficient ycbcr_coeff; enum color_depth color_depth; - enum link_rate_type link_rate; - enum link_lane_count_type lane_count; + enum link_rate_type max_link_rate; + enum link_lane_count_type max_lane_count; }; struct link_train {