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[66.187.233.206]) by smtp.gmail.com with ESMTPSA id o9sm1436509qkh.17.2015.10.05.07.22.21 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Oct 2015 07:22:22 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 4/5] qcom-scm: add support to restore secure config Date: Mon, 5 Oct 2015 10:22:10 -0400 Message-Id: <1444054931-2147-5-git-send-email-robdclark@gmail.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1444054931-2147-1-git-send-email-robdclark@gmail.com> References: <1444054931-2147-1-git-send-email-robdclark@gmail.com> Cc: Stephen Boyd , Bjorn Andersson X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Needed by OCMEM driver. Signed-off-by: Rob Clark --- drivers/firmware/qcom_scm-32.c | 20 ++++++++++++++++++++ drivers/firmware/qcom_scm-64.c | 5 +++++ drivers/firmware/qcom_scm.c | 22 ++++++++++++++++++++++ drivers/firmware/qcom_scm.h | 5 +++++ include/linux/qcom_scm.h | 3 +++ 5 files changed, 55 insertions(+) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index c1e4325..a7bf6d4 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -500,6 +500,26 @@ int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) req, req_cnt * sizeof(*req), resp, sizeof(*resp)); } +int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num) +{ + int ret, scm_ret = 0; + struct msm_scm_sec_cfg { + __le32 id; + __le32 ctx_bank_num; + } cfg; + + cfg.id = cpu_to_le32(sec_id); + cfg.ctx_bank_num = cpu_to_le32(sec_id); + + ret = qcom_scm_call(QCOM_SCM_MP_SVC, QCOM_SCM_MP_RESTORE_SEC_CFG, + &cfg, sizeof(cfg), &scm_ret, sizeof(scm_ret)); + + if (ret || scm_ret) + return ret ? ret : -EINVAL; + + return 0; +} + bool __qcom_scm_pas_supported(u32 peripheral) { __le32 out; diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index e64fd92..7329cf0f 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -62,6 +62,11 @@ int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) return -ENOTSUPP; } +int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num) +{ + return -ENOTSUPP; +} + bool __qcom_scm_pas_supported(u32 peripheral) { return false; diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 39082c1..8f43c0b 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -154,6 +154,28 @@ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) EXPORT_SYMBOL(qcom_scm_hdcp_req); /** + * qcom_scm_restore_sec_config_available() - Check if secure environment + * supports restore security config interface. + * + * Return true if restore-cfg interface is supported, false if not. + */ +bool qcom_scm_restore_sec_config_available(void) +{ + return __qcom_scm_is_call_available(QCOM_SCM_MP_SVC, + QCOM_SCM_MP_RESTORE_SEC_CFG); +} +EXPORT_SYMBOL(qcom_scm_restore_sec_config_available); + +/** + * qcom_scm_restore_sec_config() - call restore-cfg interface + */ +int qcom_scm_restore_sec_config(unsigned sec_id) +{ + return __qcom_scm_restore_sec_config(sec_id, 0); +} +EXPORT_SYMBOL(qcom_scm_restore_sec_config); + +/** * qcom_scm_pas_supported() - Check if the peripheral authentication service is * available for the given peripherial * @peripheral: peripheral id diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 220d19c..3085616 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -36,6 +36,11 @@ extern int __qcom_scm_is_call_available(u32 svc_id, u32 cmd_id); extern int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp); +#define QCOM_SCM_MP_SVC 0xc +#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x2 + +extern int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num); + #define QCOM_SCM_SVC_PIL 0x2 #define QCOM_SCM_PAS_INIT_IMAGE_CMD 0x1 #define QCOM_SCM_PAS_MEM_SETUP_CMD 0x2 diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index e407c0a..7be3d91 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -32,6 +32,9 @@ extern bool qcom_scm_hdcp_available(void); extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp); +extern bool qcom_scm_restore_sec_config_available(void); +extern int qcom_scm_restore_sec_config(unsigned sec_id); + extern bool qcom_scm_pas_supported(u32 peripheral); extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size); extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size);