From patchwork Mon Oct 5 14:22:11 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 7327781 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6AF91BF90C for ; Mon, 5 Oct 2015 14:22:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6B089206AD for ; Mon, 5 Oct 2015 14:22:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 5B450206B7 for ; Mon, 5 Oct 2015 14:22:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2985E6E8B5; Mon, 5 Oct 2015 07:22:26 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qg0-f50.google.com (mail-qg0-f50.google.com [209.85.192.50]) by gabe.freedesktop.org (Postfix) with ESMTPS id 768046E87A for ; Mon, 5 Oct 2015 07:22:24 -0700 (PDT) Received: by qgx61 with SMTP id 61so150768452qgx.3 for ; Mon, 05 Oct 2015 07:22:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=B7+yLzGlXH9i0zyQNcGn6SLNKT54Hu3f+IAK+I05ntY=; b=PUTyijG5ZFDO7DzRQalkeM1pxTF4k1NeHwx0cRx9FlUvnRrp6wsTJneDJDC9iHEuDf 1WELWB+tumzyS1RUbbgBug+FR9M1iUn+3N00ipBTz08CgrlUTlg9bNjMzz07/2v0kU16 H1Bwjgje3j5b/ctWdq+roM8xhrE1xU0w659ACQ6ByLNFAdfC9uVJYkMWeDQz17iC9OL/ YTN5qAOYVhtvJR3pZ+EAWR3YZW3TOBzdsdNo9+hY+YMWWvxaysJYfH3re7fvV8y95ehS pF40Oof2QQmEGZJMvgwQYCgAP/+jh5GcU6b/Sv32AdvWVHnYJjoeZD32DAl5zm/wL5O7 27dQ== X-Received: by 10.140.18.196 with SMTP id 62mr39222992qgf.79.1444054943600; Mon, 05 Oct 2015 07:22:23 -0700 (PDT) Received: from localhost (nat-pool-bos-t.redhat.com. [66.187.233.206]) by smtp.gmail.com with ESMTPSA id 68sm11432023qgy.16.2015.10.05.07.22.23 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Oct 2015 07:22:23 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [PATCH 5/5] qcom-scm: add OCMEM lock/unlock interface Date: Mon, 5 Oct 2015 10:22:11 -0400 Message-Id: <1444054931-2147-6-git-send-email-robdclark@gmail.com> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1444054931-2147-1-git-send-email-robdclark@gmail.com> References: <1444054931-2147-1-git-send-email-robdclark@gmail.com> Cc: Stephen Boyd , Bjorn Andersson X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Needed to enable device access to OCMEM. Signed-off-by: Rob Clark --- drivers/firmware/qcom_scm-32.c | 34 ++++++++++++++++++++++++++++++++++ drivers/firmware/qcom_scm-64.c | 11 +++++++++++ drivers/firmware/qcom_scm.c | 39 +++++++++++++++++++++++++++++++++++++++ drivers/firmware/qcom_scm.h | 7 +++++++ include/linux/qcom_scm.h | 4 ++++ 5 files changed, 95 insertions(+) diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c index a7bf6d4..dc84771b 100644 --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-32.c @@ -520,6 +520,40 @@ int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num) return 0; } +int __qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode) +{ + struct ocmem_tz_lock { + __le32 id; + __le32 offset; + __le32 size; + __le32 mode; + } request; + + request.id = cpu_to_le32(id); + request.offset = cpu_to_le32(offset); + request.size = cpu_to_le32(size); + request.mode = cpu_to_le32(mode); + + return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_LOCK_CMD, + &request, sizeof(request), NULL, 0); +} + +int __qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size) +{ + struct ocmem_tz_unlock { + __le32 id; + __le32 offset; + __le32 size; + } request; + + request.id = cpu_to_le32(id); + request.offset = cpu_to_le32(offset); + request.size = cpu_to_le32(size); + + return qcom_scm_call(QCOM_SCM_OCMEM_SVC, QCOM_SCM_OCMEM_UNLOCK_CMD, + &request, sizeof(request), NULL, 0); +} + bool __qcom_scm_pas_supported(u32 peripheral) { __le32 out; diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-64.c index 7329cf0f..0ca20a3 100644 --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-64.c @@ -67,6 +67,17 @@ int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num) return -ENOTSUPP; } +int __qcom_scm_ocmem_lock(uint32_t id, uint32_t offset, uint32_t size, + uint32_t mode) +{ + return -ENOTSUPP; +} + +int __qcom_scm_ocmem_unlock(uint32_t id, uint32_t offset, uint32_t size) +{ + return -ENOTSUPP; +} + bool __qcom_scm_pas_supported(u32 peripheral) { return false; diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 8f43c0b..0e7ce42 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -176,6 +176,45 @@ int qcom_scm_restore_sec_config(unsigned sec_id) EXPORT_SYMBOL(qcom_scm_restore_sec_config); /** + * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available + */ +bool qcom_scm_ocmem_lock_available(void) +{ + return __qcom_scm_is_call_available(QCOM_SCM_OCMEM_SVC, + QCOM_SCM_OCMEM_LOCK_CMD); +} +EXPORT_SYMBOL(qcom_scm_ocmem_lock_available); + +/** + * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM + * region to the specified initiator + * + * @id: tz initiator id + * @offset: OCMEM offset + * @size: OCMEM size + * @mode: access mode (WIDE/NARROW) + */ +int qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode) +{ + return __qcom_scm_ocmem_lock(id, offset, size, mode); +} +EXPORT_SYMBOL(qcom_scm_ocmem_lock); + +/** + * qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM + * region from the specified initiator + * + * @id: tz initiator id + * @offset: OCMEM offset + * @size: OCMEM size + */ +int qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size) +{ + return __qcom_scm_ocmem_unlock(id, offset, size); +} +EXPORT_SYMBOL(qcom_scm_ocmem_unlock); + +/** * qcom_scm_pas_supported() - Check if the peripheral authentication service is * available for the given peripherial * @peripheral: peripheral id diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 3085616..ec3435e 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -41,6 +41,13 @@ extern int __qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, extern int __qcom_scm_restore_sec_config(u32 sec_id, u32 ctx_bank_num); +#define QCOM_SCM_OCMEM_SVC 0xf +#define QCOM_SCM_OCMEM_LOCK_CMD 0x1 +#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x2 + +extern int __qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode); +extern int __qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size); + #define QCOM_SCM_SVC_PIL 0x2 #define QCOM_SCM_PAS_INIT_IMAGE_CMD 0x1 #define QCOM_SCM_PAS_MEM_SETUP_CMD 0x2 diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index 7be3d91..beadca4 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -35,6 +35,10 @@ extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, extern bool qcom_scm_restore_sec_config_available(void); extern int qcom_scm_restore_sec_config(unsigned sec_id); +extern bool qcom_scm_ocmem_lock_available(void); +extern int qcom_scm_ocmem_lock(u32 id, u32 offset, u32 size, u32 mode); +extern int qcom_scm_ocmem_unlock(u32 id, u32 offset, u32 size); + extern bool qcom_scm_pas_supported(u32 peripheral); extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size); extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size);