From patchwork Fri Oct 9 19:29:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sharma, Shashank" X-Patchwork-Id: 7363361 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 19EF39F36A for ; Fri, 9 Oct 2015 19:21:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1C024207A5 for ; Fri, 9 Oct 2015 19:21:18 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 7D1A92056D for ; Fri, 9 Oct 2015 19:21:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C7FA6E7D9; Fri, 9 Oct 2015 12:21:15 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id B54C36E7D9; Fri, 9 Oct 2015 12:21:13 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP; 09 Oct 2015 12:21:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,659,1437462000"; d="scan'208";a="823203892" Received: from shashanks-desktop.iind.intel.com ([10.223.26.81]) by orsmga002.jf.intel.com with ESMTP; 09 Oct 2015 12:21:09 -0700 From: Shashank Sharma To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, robert.bradford@intel.com, jim.bish@intel.com, matthew.d.roper@intel.com, daniel.vetter@intel.com Subject: [PATCH 14/22] drm/i915: CHV: Pipe level degamma correction Date: Sat, 10 Oct 2015 00:59:04 +0530 Message-Id: <1444418952-5671-15-git-send-email-shashank.sharma@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444418952-5671-1-git-send-email-shashank.sharma@intel.com> References: <1444418952-5671-1-git-send-email-shashank.sharma@intel.com> Cc: annie.j.matheson@intel.com, avinash.reddy.palleti@intel.com, indranil.mukherjee@intel.com, kausalmalladi@gmail.com, jesse.barnes@intel.com, gary.k.smith@intel.com, kiran.s.kumar@intel.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP CHV/BSW supports Degamma color correction, which linearizes all the non-linear color values. This will be applied before Color Transformation. This patch does the following: 1. Attach deGamma property to CRTC 2. Add the core function to program DeGamma correction values for CHV/BSW platform 2. Add DeGamma correction macros/defines Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi --- drivers/gpu/drm/i915/i915_reg.h | 6 ++ drivers/gpu/drm/i915/intel_color_manager.c | 93 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_color_manager.h | 5 ++ 3 files changed, 104 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 885ac8a..c32e35d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8050,4 +8050,10 @@ enum skl_disp_power_wells { #define _PIPE_GAMMA_BASE(pipe) \ (_PIPE3(pipe, PIPEA_CGM_GAMMA, PIPEB_CGM_GAMMA, PIPEC_CGM_GAMMA)) +#define PIPEA_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x66000) +#define PIPEB_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x68000) +#define PIPEC_CGM_DEGAMMA (VLV_DISPLAY_BASE + 0x6A000) +#define _PIPE_DEGAMMA_BASE(pipe) \ + (_PIPE3(pipe, PIPEA_CGM_DEGAMMA, PIPEB_CGM_DEGAMMA, PIPEC_CGM_DEGAMMA)) + #endif /* _I915_REG_H_ */ diff --git a/drivers/gpu/drm/i915/intel_color_manager.c b/drivers/gpu/drm/i915/intel_color_manager.c index cf381b8..bbfe185 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.c +++ b/drivers/gpu/drm/i915/intel_color_manager.c @@ -27,6 +27,93 @@ #include "intel_color_manager.h" +static int chv_set_degamma(struct drm_device *dev, + struct drm_property_blob *blob, struct drm_crtc *crtc) +{ + u16 red_fract, green_fract, blue_fract; + u32 red, green, blue; + u32 num_samples; + u32 word = 0; + u32 count = 0; + u32 cgm_control_reg = 0; + u32 cgm_degamma_reg = 0; + int length; + int ret = 0; + enum pipe pipe; + struct drm_palette *degamma_data; + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_r32g32b32 *correction_values = NULL; + + if (WARN_ON(!blob)) + return -EINVAL; + + degamma_data = (struct drm_palette *)blob->data; + pipe = to_intel_crtc(crtc)->pipe; + num_samples = degamma_data->num_samples; + length = num_samples * sizeof(struct drm_r32g32b32); + + if (num_samples == GAMMA_DISABLE_VALS) { + /* Disable DeGamma functionality on Pipe - CGM Block */ + cgm_control_reg = I915_READ(_PIPE_CGM_CONTROL(pipe)); + cgm_control_reg &= ~CGM_DEGAMMA_EN; + I915_WRITE(_PIPE_CGM_CONTROL(pipe), cgm_control_reg); + DRM_DEBUG_DRIVER("DeGamma disabled on Pipe %c\n", + pipe_name(pipe)); + ret = 0; + } else if (num_samples == CHV_DEGAMMA_MAX_VALS) { + cgm_degamma_reg = _PIPE_DEGAMMA_BASE(pipe); + + count = 0; + correction_values = (struct drm_r32g32b32 *)°amma_data->lut; + while (count < CHV_DEGAMMA_MAX_VALS) { + blue = correction_values[count].b32; + green = correction_values[count].g32; + red = correction_values[count].r32; + + if (blue > CHV_MAX_GAMMA) + blue = CHV_MAX_GAMMA; + + if (green > CHV_MAX_GAMMA) + green = CHV_MAX_GAMMA; + + if (red > CHV_MAX_GAMMA) + red = CHV_MAX_GAMMA; + + blue_fract = GET_BITS(blue, 8, 14); + green_fract = GET_BITS(green, 8, 14); + red_fract = GET_BITS(red, 8, 14); + + /* Green (29:16) and Blue (13:0) in DWORD1 */ + SET_BITS(word, green_fract, 16, 14); + SET_BITS(word, green_fract, 0, 14); + I915_WRITE(cgm_degamma_reg, word); + cgm_degamma_reg += 4; + + /* Red (13:0) to be written to DWORD2 */ + word = red_fract; + I915_WRITE(cgm_degamma_reg, word); + cgm_degamma_reg += 4; + count++; + } + + DRM_DEBUG_DRIVER("DeGamma LUT loaded for Pipe %c\n", + pipe_name(pipe)); + + /* Enable DeGamma on Pipe */ + I915_WRITE(_PIPE_CGM_CONTROL(pipe), + I915_READ(_PIPE_CGM_CONTROL(pipe)) | CGM_DEGAMMA_EN); + + DRM_DEBUG_DRIVER("DeGamma correction enabled on Pipe %c\n", + pipe_name(pipe)); + ret = 0; + } else { + DRM_ERROR("Invalid number of samples for DeGamma LUT\n"); + return -EINVAL; + } + + return ret; +} + static int chv_set_gamma(struct drm_device *dev, struct drm_property_blob *blob, struct drm_crtc *crtc) { @@ -175,4 +262,10 @@ void intel_attach_color_properties_to_crtc(struct drm_device *dev, DRM_DEBUG_DRIVER("gamma property attached to CRTC\n"); } + /* Degamma correction */ + if (config->cm_palette_before_ctm_property) { + drm_object_attach_property(mode_obj, + config->cm_palette_before_ctm_property, 0); + DRM_DEBUG_DRIVER("degamma property attached to CRTC\n"); + } } diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index de706d9..77a2119 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -63,5 +63,10 @@ #define CHV_GAMMA_SHIFT_GREEN 16 #define CHV_MAX_GAMMA ((1 << 24) - 1) +/* Degamma on CHV */ +#define CHV_DEGAMMA_MSB_SHIFT 2 +#define CHV_DEGAMMA_GREEN_SHIFT 16 + /* CHV CGM Block */ #define CGM_GAMMA_EN (1 << 2) +#define CGM_DEGAMMA_EN (1 << 0)