From patchwork Tue Oct 13 12:39:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sharma, Shashank" X-Patchwork-Id: 7384731 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0B03EBEEA4 for ; Tue, 13 Oct 2015 12:33:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 160D7209AA for ; Tue, 13 Oct 2015 12:32:59 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 28AD8209A6 for ; Tue, 13 Oct 2015 12:32:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0377F7A157; Tue, 13 Oct 2015 05:32:55 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id C78637A160; Tue, 13 Oct 2015 05:32:53 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP; 13 Oct 2015 05:32:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,678,1437462000"; d="scan'208";a="825802085" Received: from shashanks-desktop.iind.intel.com ([10.223.26.81]) by fmsmga002.fm.intel.com with ESMTP; 13 Oct 2015 05:32:08 -0700 From: Shashank Sharma To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, emil.l.velikov@gmail.com, matthew.d.roper@intel.com, robert.bradford@intel.com, jim.bish@intel.com Subject: [PATCH v5 18/22] drm/i915: BDW: Load gamma correction values Date: Tue, 13 Oct 2015 18:09:53 +0530 Message-Id: <1444739997-24831-19-git-send-email-shashank.sharma@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1444739997-24831-1-git-send-email-shashank.sharma@intel.com> References: <1444739997-24831-1-git-send-email-shashank.sharma@intel.com> Cc: annie.j.matheson@intel.com, avinash.reddy.palleti@intel.com, indranil.mukherjee@intel.com, kausalmalladi@gmail.com, kiran.s.kumar@intel.com, daniel.vetter@intel.com, =gary.k.smith@intel.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP I915 color manager registers pipe gamma correction as palette correction after CTM property. For BDW and higher platforms, split gamma correction is the best gamma correction. This patch adds the no of coefficients(512) for split gamma correction as "num_samples_after_ctm" parameter in device info structures, for all of those. Signed-off-by: Shashank Sharma Signed-off-by: Kausal Malladi --- drivers/gpu/drm/i915/i915_drv.c | 7 +++++++ drivers/gpu/drm/i915/intel_color_manager.h | 3 +++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 6adf002..8beac5c 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -302,6 +302,7 @@ static const struct intel_device_info intel_broadwell_d_info = { .gen = 8, .num_pipes = 3, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -314,6 +315,7 @@ static const struct intel_device_info intel_broadwell_m_info = { .gen = 8, .is_mobile = 1, .num_pipes = 3, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -326,6 +328,7 @@ static const struct intel_device_info intel_broadwell_gt3d_info = { .gen = 8, .num_pipes = 3, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -338,6 +341,7 @@ static const struct intel_device_info intel_broadwell_gt3m_info = { .gen = 8, .is_mobile = 1, .num_pipes = 3, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -363,6 +367,7 @@ static const struct intel_device_info intel_skylake_info = { .gen = 9, .num_pipes = 3, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -376,6 +381,7 @@ static const struct intel_device_info intel_skylake_gt3_info = { .gen = 9, .num_pipes = 3, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, .has_llc = 1, .has_ddi = 1, .has_fpga_dbg = 1, @@ -389,6 +395,7 @@ static const struct intel_device_info intel_broxton_info = { .gen = 9, .need_gfx_hws = 1, .has_hotplug = 1, .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, + .num_samples_after_ctm = BDW_SPLITGAMMA_MAX_VALS, .num_pipes = 3, .has_ddi = 1, .has_fpga_dbg = 1, diff --git a/drivers/gpu/drm/i915/intel_color_manager.h b/drivers/gpu/drm/i915/intel_color_manager.h index 7b96512..271246a 100644 --- a/drivers/gpu/drm/i915/intel_color_manager.h +++ b/drivers/gpu/drm/i915/intel_color_manager.h @@ -89,3 +89,6 @@ #define CGM_GAMMA_EN (1 << 2) #define CGM_CSC_EN (1 << 1) #define CGM_DEGAMMA_EN (1 << 0) + +/* Gamma on BDW */ +#define BDW_SPLITGAMMA_MAX_VALS 512