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[RFCv0,8/8] freedreno/ir3: hack for mismatch on varying slots for glsl->tgsi->nir vs glsl->nir

Message ID 1445284081-29532-9-git-send-email-robdclark@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Rob Clark Oct. 19, 2015, 7:48 p.m. UTC 
Complete hack just for debugging.  It isn't intended that mixing and
matching glsl->tgsi->nir vs glsl->nir between shader stages should
actually work.
---
 src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c | 6 ++++++
 1 file changed, 6 insertions(+)
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Patch

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index 2b9a841..317ed79 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -2232,6 +2232,12 @@  setup_output(struct ir3_compile *ctx, nir_variable *out)
 	unsigned slot = out->data.location;
 	unsigned comp = 0;
 
+	// XXX temporary hack for NIR vs and TGSI fs.. since there is
+	// some disagreement about varying slots..
+	if (ctx->so->shader->nir)
+		if (slot >= VARYING_SLOT_VAR0)
+			slot += 9;
+
 	DBG("; out: slot=%u, len=%ux%u, drvloc=%u",
 			slot, array_len, ncomp, n);