From patchwork Tue Oct 20 12:34:51 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sharma, Shashank" X-Patchwork-Id: 7446911 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 8A0F8BF90C for ; Tue, 20 Oct 2015 12:27:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B2B6520764 for ; Tue, 20 Oct 2015 12:27:34 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id C654E206B2 for ; Tue, 20 Oct 2015 12:27:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B21236EC1D; Tue, 20 Oct 2015 05:27:32 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id A5B546EC16; Tue, 20 Oct 2015 05:27:31 -0700 (PDT) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP; 20 Oct 2015 05:27:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,707,1437462000"; d="scan'208";a="831177559" Received: from shashanks-desktop.iind.intel.com ([10.223.26.81]) by fmsmga002.fm.intel.com with ESMTP; 20 Oct 2015 05:27:27 -0700 From: Shashank Sharma To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, emil.l.velikov@gmail.com, matthew.d.roper@intel.com, robert.bradford@intel.com, jim.bish@intel.com Subject: [PATCH v7 24/25] drm/i915: disable plane gamma Date: Tue, 20 Oct 2015 18:04:51 +0530 Message-Id: <1445344492-8296-25-git-send-email-shashank.sharma@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1445344492-8296-1-git-send-email-shashank.sharma@intel.com> References: <1445344492-8296-1-git-send-email-shashank.sharma@intel.com> Cc: annie.j.matheson@intel.com, avinash.reddy.palleti@intel.com, indranil.mukherjee@intel.com, kausalmalladi@gmail.com, gary.k.smith@intel.com, daniel.vetter@intel.com, kiran.s.kumar@intel.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In plane enabling sequence, plane gamma bit is by default enabled. Plane gamma gets higher priority than pipe gamma, if both enabled. This patch disables plane gamma from sequence. If required, plane gamma can be enabled via the color manager drm interface. Signed-off-by: Shashank Sharma Signed-off-by: Kumar, Kiran S --- drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915/intel_sprite.c | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 61562a3..72b701a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2820,7 +2820,7 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc, pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); - dspcntr = DISPPLANE_GAMMA_ENABLE; + dspcntr = (DISPPLANE_GAMMA_ENABLE | PLANE_CTL_PLANE_GAMMA_DISABLE); dspcntr |= DISPLAY_PLANE_ENABLE; diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 56dc132..6e2be1c 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -204,7 +204,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc, plane_ctl = PLANE_CTL_ENABLE | PLANE_CTL_PIPE_GAMMA_ENABLE | - PLANE_CTL_PIPE_CSC_ENABLE; + PLANE_CTL_PIPE_CSC_ENABLE | + PLANE_CTL_PLANE_GAMMA_DISABLE; plane_ctl |= skl_plane_ctl_format(fb->pixel_format); plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); @@ -409,7 +410,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, * Enable gamma to match primary/cursor plane behaviour. * FIXME should be user controllable via propertiesa. */ - sprctl |= SP_GAMMA_ENABLE; + sprctl |= (SP_GAMMA_ENABLE | PLANE_CTL_PLANE_GAMMA_DISABLE); if (obj->tiling_mode != I915_TILING_NONE) sprctl |= SP_TILED; @@ -528,7 +529,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, * Enable gamma to match primary/cursor plane behaviour. * FIXME should be user controllable via propertiesa. */ - sprctl |= SPRITE_GAMMA_ENABLE; + sprctl |= (SPRITE_GAMMA_ENABLE | PLANE_CTL_PLANE_GAMMA_DISABLE); if (obj->tiling_mode != I915_TILING_NONE) sprctl |= SPRITE_TILED;