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[74.96.105.49]) by smtp.gmail.com with ESMTPSA id m127sm6292214ywe.8.2015.10.21.09.12.02 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 21 Oct 2015 09:12:03 -0700 (PDT) From: Alex Deucher X-Google-Original-From: Alex Deucher To: dri-devel@lists.freedesktop.org Subject: [PATCH 04/10] drm/amdgpu: add DCE support for Stoney Date: Wed, 21 Oct 2015 12:11:48 -0400 Message-Id: <1445443914-31602-5-git-send-email-alexander.deucher@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1445443914-31602-1-git-send-email-alexander.deucher@amd.com> References: <1445443914-31602-1-git-send-email-alexander.deucher@amd.com> Cc: Alex Deucher , Samuel Li X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Samuel Li Stoney is DCE 11.x. Signed-off-by: Samuel Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index bdafeb2..444d930 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -126,6 +126,13 @@ static const u32 cz_mgcg_cgcg_init[] = mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, }; +static const u32 stoney_golden_settings_a11[] = +{ + mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, + mmFBC_MISC, 0x1f311fff, 0x14302000, +}; + + static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { @@ -137,6 +144,11 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) cz_golden_settings_a11, (const u32)ARRAY_SIZE(cz_golden_settings_a11)); break; + case CHIP_STONEY: + amdgpu_program_register_sequence(adev, + stoney_golden_settings_a11, + (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + break; default: break; } @@ -2425,7 +2437,7 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) /* XXX need to determine what plls are available on each DCE11 part */ pll_in_use = amdgpu_pll_get_use_mask(crtc); - if (adev->asic_type == CHIP_CARRIZO) { + if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) { if (!(pll_in_use & (1 << ATOM_PPLL1))) return ATOM_PPLL1; if (!(pll_in_use & (1 << ATOM_PPLL0))) @@ -2930,6 +2942,11 @@ static int dce_v11_0_early_init(void *handle) adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; break; + case CHIP_STONEY: + adev->mode_info.num_crtc = 2; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 9; + break; default: /* FIXME: not supported yet */ return -EINVAL;