From patchwork Fri Oct 30 14:20:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 7528081 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 6DB16BEEA4 for ; Fri, 30 Oct 2015 16:11:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 81C12204D2 for ; Fri, 30 Oct 2015 16:11:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8CEDC20456 for ; Fri, 30 Oct 2015 16:11:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A50286ED0A; Fri, 30 Oct 2015 09:10:55 -0700 (PDT) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.free-electrons.com (down.free-electrons.com [37.187.137.238]) by gabe.freedesktop.org (Postfix) with ESMTP id 8D1576ECBF for ; Fri, 30 Oct 2015 07:27:03 -0700 (PDT) Received: by mail.free-electrons.com (Postfix, from userid 110) id B18331DAA; Fri, 30 Oct 2015 15:21:54 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (AToulouse-657-1-1002-69.w90-55.abo.wanadoo.fr [90.55.204.69]) by mail.free-electrons.com (Postfix) with ESMTPSA id 809031DAB; Fri, 30 Oct 2015 15:21:14 +0100 (CET) From: Maxime Ripard To: Mike Turquette , Stephen Boyd , David Airlie , Thierry Reding Subject: [PATCH 09/19] drm: sun4i: Add DT bindings documentation Date: Fri, 30 Oct 2015 15:20:55 +0100 Message-Id: <1446214865-3972-10-git-send-email-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.6.2 In-Reply-To: <1446214865-3972-1-git-send-email-maxime.ripard@free-electrons.com> References: <1446214865-3972-1-git-send-email-maxime.ripard@free-electrons.com> X-Mailman-Approved-At: Fri, 30 Oct 2015 09:08:28 -0700 Cc: Thomas Petazzoni , devicetree@vger.kernel.org, Wynter Woods , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Maxime Ripard , Hans de Goede , linux-sunxi@googlegroups.com, Laurent Pinchart , Alexander Kaplan , Chen-Yu Tsai , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The display pipeline of the Allwinner A10 is involving several loosely coupled components. Add a documentation for the bindings. Signed-off-by: Maxime Ripard --- .../devicetree/bindings/drm/sunxi/sun4i-drm.txt | 122 +++++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 Documentation/devicetree/bindings/drm/sunxi/sun4i-drm.txt diff --git a/Documentation/devicetree/bindings/drm/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/drm/sunxi/sun4i-drm.txt new file mode 100644 index 000000000000..dbdccef787b4 --- /dev/null +++ b/Documentation/devicetree/bindings/drm/sunxi/sun4i-drm.txt @@ -0,0 +1,122 @@ +Allwinner A10 Display Pipeline +============================== + +The Allwinner A10 Display pipeline is composed of several components +that are going to be documented below: + +TV Encoder +---------- + +The TV Encoder supports the composite and VGA output. It is one end of +the pipeline. + +Required properties: + - compatible: value should be "allwinner,sun4i-a10-tv-encoder". + - reg: base address and size of memory-mapped region + - clocks: the clocks driving the TV encoder + +TCON +---- + +The TCON acts as a CRTC and encoder for RGB / LVDS interfaces. + +Required properties: + - compatible: value should be "allwinner,sun4i-a10-tcon". + - reg: base address and size of memory-mapped region + - interrupts: interrupt associated to this IP + - clocks: phandles to the clocks feeding the TCON. Three are needed: + - 'ahb': the interface clocks + - 'tcon-ch0': The clock driving the TCON channel 0 + - 'tcon-ch1': The clock driving the TCON channel 0 + + - clock-names: the clock names mentionned above + - clock-output-names: Name of the pixel clock created + + +Display Engine Backend +---------------------- + +The display engine backend exposes layers and sprites to the +system. It's split into two components, the frontend and backend, the +frontend doing formats conversion, scaling, deinterlacing, while the +backend actually manages the layers. + +Required properties: + - compatible: value must be one of: + * allwinner,sun5i-a13-display-engine + + - reg: base address and size of the memory-mapped region. Two are needed: + * backend0: registers of the display engine backend + * frontend0: registers of the display engine frontend + - reg_names: the region names mentionned above. + + - interrupts: frontend interrupt phandle + + - clocks: phandles to the clocks feeding the frontend and backend + * backend0-bus: the backend interface clock + * backend0-mod: the backend module clock + * backend0-ram: the backend DRAM clock + * frontend0-bus: the frontend interface clock + * frontend0-mod: the frontend module clock + * frontend0-ram: the frontend DRAM clock + - clock-names: the clock names mentionned above + + - resets: phandles to the reset controllers. Two are needed: + * backend0: backend reset controller + * frontend0: frontend reset controller + - reset-names: the reset names mentionned above + + - allwinner,tcon: phandle to the TCON in our pipeline + +Optional properties: + - allwinner,tv-encoder: phandle to the TV Encoder in our pipeline + - allwinner,panel: phandle to the panel used in our RGB interface + +Example: + +panel: panel { + compatible = "olimex,lcd-olinuxino-43-ts"; +}; + +tve: encoder@01c0a000 { + compatible = "allwinner,sun4i-a10-tv-encoder"; + reg = <0x01c0a000 0x1000>; + clocks = <&ahb_gates 34>; +}; + +tcon: lcd-controller@01c0c000 { + compatible = "allwinner,sun4i-a10-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + clocks = <&ahb_gates 36>, + <&tcon_ch0_clk>, + <&tcon_ch1_clk>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon-pixel-clock"; +}; + +de: display-engine@01e00000 { + compatible = "allwinner,sun5i-a13-display-engine"; + reg = <0x01e00000 0x20000>, + <0x01e60000 0x10000>; + reg-names = "frontend0", + "backend0"; + interrupts = <47>; + interrupt-names = "engine0"; + clocks = <&ahb_gates 46>, <&de_fe_clk>, + <&dram_gates 25>, <&ahb_gates 44>, + <&de_be_clk>, <&dram_gates 26>; + clock-names = "frontend0-bus", "frontend0-mod", + "frontend0-ram", "backend0-bus", + "backend0-mod", "backend0-ram"; + resets = <&de_fe_clk>, + <&de_be_clk>; + reset-names = "frontend0", + "backend0"; + + allwinner,tcon = <&tcon>; + allwinner,tv-encoder = <&tve>; + allwinner,panel = <&panel>; +};