From patchwork Thu Nov 12 06:18:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 7599571 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 24B3BBF90C for ; Thu, 12 Nov 2015 06:19:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1178C207D5 for ; Thu, 12 Nov 2015 06:19:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 1DF54207DB for ; Thu, 12 Nov 2015 06:19:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 300977A097; Wed, 11 Nov 2015 22:19:12 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qg0-f42.google.com (mail-qg0-f42.google.com [209.85.192.42]) by gabe.freedesktop.org (Postfix) with ESMTPS id 47CA57A092 for ; Wed, 11 Nov 2015 22:19:10 -0800 (PST) Received: by qgad10 with SMTP id d10so40910848qga.3 for ; Wed, 11 Nov 2015 22:19:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YWBdo3HiIC5jk9FBgldStaCKmkcbfgFFaG2DcFAFZJg=; b=MCXGYcPr5MWfic1rPmpRbqaBb+L/bQQ3I8Ne6n93amHLgVI/aoc9rUjbE+x5WXuDgC nwInOzyomFOn0sDcxFgMXKtxDgD42rnG9xtkW67tYwXISZBJwFjPyUzazf6DqbIOcvvC IfQnpoaZ79L42AiAE3H3NF271czRwuPhA/dOsEIJAlIQK8WM7Se/DgP71tKtxbzb7Ytc vsknW1U14OgsQC07ASp/e08XeWWJbZY1+WlFVB+ypfGzg4cyVeE/W9cheuJty+3IMfLU 5h3lsC1DUbdRiRUxTGFl9vbafMNuUk86weWKReOCLT7ZlsoY6WQTwP4vGQ5UPZwJxuLA 4cRQ== X-Received: by 10.140.152.83 with SMTP id 80mr15975587qhy.8.1447309149262; Wed, 11 Nov 2015 22:19:09 -0800 (PST) Received: from localhost.localdomain (static-74-96-105-49.washdc.fios.verizon.net. [74.96.105.49]) by smtp.gmail.com with ESMTPSA id 202sm3693748qhc.49.2015.11.11.22.19.08 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 11 Nov 2015 22:19:08 -0800 (PST) From: Alex Deucher X-Google-Original-From: Alex Deucher To: dri-devel@lists.freedesktop.org Subject: [PATCH 16/51] drm/amd/powerplay: implement functions of amd_powerplay_func Date: Thu, 12 Nov 2015 01:18:06 -0500 Message-Id: <1447309121-2480-17-git-send-email-alexander.deucher@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1447309121-2480-1-git-send-email-alexander.deucher@amd.com> References: <1447309121-2480-1-git-send-email-alexander.deucher@amd.com> Cc: Rex Zhu X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rex Zhu This is the common interface for interacting with the powerplay module. v2: squash in fixes Signed-off-by: Rex Zhu Acked-by: Jammy Zhou Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 191 ++++++++++++++++++++++++-- 1 file changed, 183 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c index 1964a2a..66ccfc0 100644 --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c @@ -27,6 +27,8 @@ #include "amd_shared.h" #include "amd_powerplay.h" #include "pp_instance.h" +#include "power_state.h" +#include "eventmanager.h" static int pp_early_init(void *handle) { @@ -177,11 +179,31 @@ static int pp_set_powergating_state(void *handle, static int pp_suspend(void *handle) { + struct pp_instance *pp_handle; + struct pp_eventmgr *eventmgr; + struct pem_event_data event_data = { {0} }; + + if (handle == NULL) + return -EINVAL; + + pp_handle = (struct pp_instance *)handle; + eventmgr = pp_handle->eventmgr; + pem_handle_event(eventmgr, AMD_PP_EVENT_SUSPEND, &event_data); return 0; } static int pp_resume(void *handle) { + struct pp_instance *pp_handle; + struct pp_eventmgr *eventmgr; + struct pem_event_data event_data = { {0} }; + + if (handle == NULL) + return -EINVAL; + + pp_handle = (struct pp_instance *)handle; + eventmgr = pp_handle->eventmgr; + pem_handle_event(eventmgr, AMD_PP_EVENT_RESUME, &event_data); return 0; } @@ -215,45 +237,198 @@ static int pp_dpm_fw_loading_complete(void *handle) static int pp_dpm_force_performance_level(void *handle, enum amd_dpm_forced_level level) { + struct pp_instance *pp_handle; + struct pp_hwmgr *hwmgr; + + if (handle == NULL) + return -EINVAL; + + pp_handle = (struct pp_instance *)handle; + + hwmgr = pp_handle->hwmgr; + + if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || + hwmgr->hwmgr_func->force_dpm_level == NULL) + return -EINVAL; + + hwmgr->hwmgr_func->force_dpm_level(hwmgr, level); + return 0; } + static enum amd_dpm_forced_level pp_dpm_get_performance_level( void *handle) { - return 0; + struct pp_hwmgr *hwmgr; + + if (handle == NULL) + return -EINVAL; + + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + if (hwmgr == NULL) + return -EINVAL; + + return (((struct pp_instance *)handle)->hwmgr->dpm_level); } + static int pp_dpm_get_sclk(void *handle, bool low) { - return 0; + struct pp_hwmgr *hwmgr; + + if (handle == NULL) + return -EINVAL; + + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || + hwmgr->hwmgr_func->get_sclk == NULL) + return -EINVAL; + + return hwmgr->hwmgr_func->get_sclk(hwmgr, low); } + static int pp_dpm_get_mclk(void *handle, bool low) { - return 0; + struct pp_hwmgr *hwmgr; + + if (handle == NULL) + return -EINVAL; + + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || + hwmgr->hwmgr_func->get_mclk == NULL) + return -EINVAL; + + return hwmgr->hwmgr_func->get_mclk(hwmgr, low); } + static int pp_dpm_powergate_vce(void *handle, bool gate) { - return 0; + struct pp_hwmgr *hwmgr; + + if (handle == NULL) + return -EINVAL; + + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || + hwmgr->hwmgr_func->powergate_vce == NULL) + return -EINVAL; + + return hwmgr->hwmgr_func->powergate_vce(hwmgr, gate); } + static int pp_dpm_powergate_uvd(void *handle, bool gate) { - return 0; + struct pp_hwmgr *hwmgr; + + if (handle == NULL) + return -EINVAL; + + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || + hwmgr->hwmgr_func->powergate_uvd == NULL) + return -EINVAL; + + return hwmgr->hwmgr_func->powergate_uvd(hwmgr, gate); +} + +static enum PP_StateUILabel power_state_convert(enum amd_pm_state_type state) +{ + switch (state) { + case POWER_STATE_TYPE_BATTERY: + return PP_StateUILabel_Battery; + case POWER_STATE_TYPE_BALANCED: + return PP_StateUILabel_Balanced; + case POWER_STATE_TYPE_PERFORMANCE: + return PP_StateUILabel_Performance; + default: + return PP_StateUILabel_None; + } } int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input, void *output) { - return 0; + int ret = 0; + struct pp_instance *pp_handle; + struct pem_event_data data = { {0} }; + + pp_handle = (struct pp_instance *)handle; + + if (pp_handle == NULL) + return -EINVAL; + + switch (event_id) { + case AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE: + ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); + break; + case AMD_PP_EVENT_ENABLE_USER_STATE: + { + enum amd_pm_state_type ps; + + if (input == NULL) + return -EINVAL; + ps = *(unsigned long *)input; + + data.requested_ui_label = power_state_convert(ps); + ret = pem_handle_event(pp_handle->eventmgr, event_id, &data); + } + break; + default: + break; + } + return ret; } + enum amd_pm_state_type pp_dpm_get_current_power_state(void *handle) { - return 0; + struct pp_hwmgr *hwmgr; + struct pp_power_state *state; + + if (handle == NULL) + return -EINVAL; + + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + if (hwmgr == NULL || hwmgr->current_ps == NULL) + return -EINVAL; + + state = hwmgr->current_ps; + + switch (state->classification.ui_label) { + case PP_StateUILabel_Battery: + return POWER_STATE_TYPE_BATTERY; + case PP_StateUILabel_Balanced: + return POWER_STATE_TYPE_BALANCED; + case PP_StateUILabel_Performance: + return POWER_STATE_TYPE_PERFORMANCE; + default: + return POWER_STATE_TYPE_DEFAULT; + } } + static void pp_debugfs_print_current_performance_level(void *handle, struct seq_file *m) { - return; + struct pp_hwmgr *hwmgr; + + if (handle == NULL) + return; + + hwmgr = ((struct pp_instance *)handle)->hwmgr; + + if (hwmgr == NULL || hwmgr->hwmgr_func == NULL || + hwmgr->hwmgr_func->print_current_perforce_level == NULL) + return; + + hwmgr->hwmgr_func->print_current_perforce_level(hwmgr, m); } + const struct amd_powerplay_funcs pp_dpm_funcs = { .get_temperature = NULL, .load_firmware = pp_dpm_load_fw,