From patchwork Thu Nov 12 06:18:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 7599881 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A8330BF90C for ; Thu, 12 Nov 2015 06:20:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1B800207DB for ; Thu, 12 Nov 2015 06:20:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 0C7DB207D0 for ; Thu, 12 Nov 2015 06:20:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 21D2F7A112; Wed, 11 Nov 2015 22:19:31 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qk0-f174.google.com (mail-qk0-f174.google.com [209.85.220.174]) by gabe.freedesktop.org (Postfix) with ESMTPS id C14077A08A for ; Wed, 11 Nov 2015 22:19:28 -0800 (PST) Received: by qkcl124 with SMTP id l124so20254088qkc.3 for ; Wed, 11 Nov 2015 22:19:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OQdM7GsHibQiyPgwKSgoZqs10paF/9j+dZrZfYrpGr4=; b=ofXItWjfM/l2glwRusPiKHmtokmVF1G/CrGKGy6aIuCNggMWVVF8jyPhFjF7hCK3y6 jJHVBmSLzF/2d64a0klPurnBI9JBSTzhQ2nWVXt+Ud0G//EacXr4Ps74Q8Is+6aZ4xi8 SDalG3g95yO8/C7WqNGp6rLJOv3Xxo+uqikxhf6yNhKqa/eiG/EHn7NGBCbRKg3M16f9 Uhwd22EbeEvj47zA4e7b77cJg+NYsKl/h1fTHSvob+58oYMCz6WAitJe3GyTcx4IoHdz JUUN6DpPvR8KzMywbYNkGhisDqcDt9Qi+iyZ6pc7X4avebmz35tqBS92A1A5KomXBvOv EMhA== X-Received: by 10.55.197.3 with SMTP id p3mr14293756qki.11.1447309167492; Wed, 11 Nov 2015 22:19:27 -0800 (PST) Received: from localhost.localdomain (static-74-96-105-49.washdc.fios.verizon.net. [74.96.105.49]) by smtp.gmail.com with ESMTPSA id 202sm3693748qhc.49.2015.11.11.22.19.27 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 11 Nov 2015 22:19:27 -0800 (PST) From: Alex Deucher X-Google-Original-From: Alex Deucher To: dri-devel@lists.freedesktop.org Subject: [PATCH 47/51] drm/amd/powerplay: implement new funcs to check current states for tonga. Date: Thu, 12 Nov 2015 01:18:37 -0500 Message-Id: <1447309121-2480-48-git-send-email-alexander.deucher@amd.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1447309121-2480-1-git-send-email-alexander.deucher@amd.com> References: <1447309121-2480-1-git-send-email-alexander.deucher@amd.com> Cc: Rex Zhu X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.5 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Rex Zhu Implement the new callbacks for tonga. Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Reviewed-by: Jammy Zhou --- drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 62 +++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c index 088b5bf..9a1e8bf 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c @@ -5935,6 +5935,66 @@ int tonga_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, return 0; } +bool tonga_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) +{ + struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); + bool is_update_required = false; + struct cgs_display_info info = {0,0,NULL}; + + cgs_get_active_displays_info(hwmgr->device, &info); + + if (data->display_timing.num_existing_displays != info.display_count) + is_update_required = true; +/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL + if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { + cgs_get_min_clock_settings(hwmgr->device, &min_clocks); + if(min_clocks.engineClockInSR != data->display_timing.minClockInSR) + is_update_required = true; +*/ + return is_update_required; +} + +static inline bool tonga_are_power_levels_equal(const struct tonga_performance_level *pl1, + const struct tonga_performance_level *pl2) +{ + return ((pl1->memory_clock == pl2->memory_clock) && + (pl1->engine_clock == pl2->engine_clock) && + (pl1->pcie_gen == pl2->pcie_gen) && + (pl1->pcie_lane == pl2->pcie_lane)); +} + +int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) +{ + const struct tonga_power_state *psa = cast_const_phw_tonga_power_state(pstate1); + const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2); + int i; + + if (pstate1 == NULL || pstate2 == NULL || equal == NULL) + return -EINVAL; + + /* If the two states don't even have the same number of performance levels they cannot be the same state. */ + if (psa->performance_level_count != psb->performance_level_count) { + *equal = false; + return 0; + } + + for (i = 0; i < psa->performance_level_count; i++) { + if (!tonga_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { + /* If we have found even one performance level pair that is different the states are different. */ + *equal = false; + return 0; + } + } + + /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ + *equal = ((psa->uvd_clocks.VCLK == psb->uvd_clocks.VCLK) && (psa->uvd_clocks.DCLK == psb->uvd_clocks.DCLK)); + *equal &= ((psa->vce_clocks.EVCLK == psb->vce_clocks.EVCLK) && (psa->vce_clocks.ECCLK == psb->vce_clocks.ECCLK)); + *equal &= (psa->sclk_threshold == psb->sclk_threshold); + *equal &= (psa->acp_clk == psb->acp_clk); + + return 0; +} + static const struct pp_hwmgr_func tonga_hwmgr_funcs = { .backend_init = &tonga_hwmgr_backend_init, .backend_fini = &tonga_hwmgr_backend_fini, @@ -5968,6 +6028,8 @@ static const struct pp_hwmgr_func tonga_hwmgr_funcs = { .set_fan_speed_rpm = tonga_fan_ctrl_set_fan_speed_rpm, .uninitialize_thermal_controller = tonga_thermal_ctrl_uninitialize_thermal_controller, .register_internal_thermal_interrupt = tonga_register_internal_thermal_interrupt, + .check_smc_update_required_for_display_configuration = tonga_check_smc_update_required_for_display_configuration, + .check_states_equal = tonga_check_states_equal, }; int tonga_hwmgr_init(struct pp_hwmgr *hwmgr)