From patchwork Thu Nov 19 03:35:21 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Zhong X-Patchwork-Id: 7656031 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1CD85BF90C for ; Thu, 19 Nov 2015 08:51:53 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4BD3820613 for ; Thu, 19 Nov 2015 08:51:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 3BA3020437 for ; Thu, 19 Nov 2015 08:51:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5644F7A00E; Thu, 19 Nov 2015 00:51:44 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-ig0-f177.google.com (mail-ig0-f177.google.com [209.85.213.177]) by gabe.freedesktop.org (Postfix) with ESMTPS id 570196E894 for ; Wed, 18 Nov 2015 19:37:14 -0800 (PST) Received: by igvi2 with SMTP id i2so3327878igv.0 for ; Wed, 18 Nov 2015 19:37:13 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xXWT1kybFzT+90XwVL1uAys/lHWDngtaqUQsAzz1JJs=; b=HL1sW2yNKtzj4sXs5tau4DBgLp63KhdPTxgL7IbGpSF3IvsgoTS31yOm31mNEzWPsc xNwo5R/8/JiepBkza7fkKbrU+d42XrFSXda/KdpbHKKfF3hNH1s/NHhruBBFl0q5ky/n r/BhQztONd8gJJpcQPAOnzvKbFfveL7F4c4xCb7bHE/OvsZwbIJZQduyygY7CVE6nhTn Xp/E1Rq5VxEe91OviXr/LPyClMbBWmRQLIN9VgQnvnvHlqEN4WCpEdDlXQl6SDQO5N4i 3a/aUgvhCPnkQnVWUHqgB2W9vQBax7uuIeE8oezkMMnNzaQ0DjYQ3b/SS37B19DDHTCp 4Lrg== X-Received: by 10.50.28.17 with SMTP id x17mr554243igg.47.1447904233765; Wed, 18 Nov 2015 19:37:13 -0800 (PST) Received: from localhost.localdomain ([45.74.60.49]) by smtp.gmail.com with ESMTPSA id n3sm11392131iga.0.2015.11.18.19.37.03 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Nov 2015 19:37:12 -0800 (PST) From: Chris Zhong To: heiko@sntech.de, linux-rockchip@lists.infradead.org, Mark Yao Subject: [PATCH v3 03/12] drm/rockchip: return a true clock rate to adjusted_mode Date: Thu, 19 Nov 2015 11:35:21 +0800 Message-Id: <1447904131-29328-4-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 2.6.3 In-Reply-To: <1447904131-29328-1-git-send-email-zyw@rock-chips.com> References: <1447904131-29328-1-git-send-email-zyw@rock-chips.com> X-Mailman-Approved-At: Thu, 19 Nov 2015 00:51:42 -0800 Cc: Chris Zhong , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Sometimes the clock driver can not set a accurate clock_rate for vop, get the true rate of vop_dclk and set it back to adjusted_mode, since the mipi dsi driver need to use the clock to make the calculation of Blanking. Signed-off-by: Chris Zhong --- Changes in v3: None Changes in v2: None drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c index 5d8ae5e..9986b311ed 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c @@ -1232,6 +1232,12 @@ static int vop_crtc_mode_set(struct drm_crtc *crtc, reset_control_deassert(vop->dclk_rst); clk_set_rate(vop->dclk, adjusted_mode->clock * 1000); + + /* + * Sometimes the clock driver can not set a accurate clock_rate for vop, + * get the true rate of vop_dclk and set it back to adjusted_mode. + */ + adjusted_mode->clock = clk_get_rate(vop->dclk) / 1000; out: ret_clk = clk_enable(vop->dclk); if (ret_clk < 0) {