From patchwork Wed Dec 16 12:21:44 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 7861171 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0C20FBEEE1 for ; Wed, 16 Dec 2015 12:22:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C7351203EC for ; Wed, 16 Dec 2015 12:22:24 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 0718B203F3 for ; Wed, 16 Dec 2015 12:22:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 91A6F6E8B5; Wed, 16 Dec 2015 04:22:18 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout4.w1.samsung.com (mailout4.w1.samsung.com [210.118.77.14]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9CEA16E8B2 for ; Wed, 16 Dec 2015 04:22:16 -0800 (PST) Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NZG00FRVAD14480@mailout4.w1.samsung.com> for dri-devel@lists.freedesktop.org; Wed, 16 Dec 2015 12:22:13 +0000 (GMT) X-AuditID: cbfec7f4-f79026d00000418a-3d-56715775fef4 Received: from eusync4.samsung.com ( [203.254.199.214]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id B0.19.16778.57751765; Wed, 16 Dec 2015 12:22:13 +0000 (GMT) Received: from amdc1339.digital.local ([106.116.147.30]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NZG0012YACWHH70@eusync4.samsung.com>; Wed, 16 Dec 2015 12:22:13 +0000 (GMT) From: Marek Szyprowski To: dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 3/7] drm/exynos: mixer: set window priority based on zpos Date: Wed, 16 Dec 2015 13:21:44 +0100 Message-id: <1450268508-15028-4-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.2 In-reply-to: <1450268508-15028-1-git-send-email-m.szyprowski@samsung.com> References: <1450268508-15028-1-git-send-email-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrKLMWRmVeSWpSXmKPExsVy+t/xa7ql4YVhBgv26FvcWneO1WLjjPWs Fle+vmez2PlgF7vFpPsTWCxe3LvIYvH6haHFjPP7mCzWHrnLbjFj8ks2i7bVH1gduD3udx9n 8vh3jN1j56S9TB59W1YxenzeJBfAGsVlk5Kak1mWWqRvl8CV8WX2a8aCY9oV96ddYWpgXKjS xcjBISFgIrFzE2sXIyeQKSZx4d56ti5GLg4hgaWMEt8azjFDOE1MElMvNLOBVLEJGEp0ve0C s0UE3CSaDs9kBSliFuhjlmhqfgiWEBbwkZjS+p0VZAOLgKrEg18eIGFeAQ+JZV8geiUE5CT+ v1zBBGJzCnhKrD0+kx3EFgKqebB6B/MERt4FjAyrGEVTS5MLipPScw31ihNzi0vz0vWS83M3 MUIC78sOxsXHrA4xCnAwKvHwXogsCBNiTSwrrsw9xCjBwawkwvtQrjBMiDclsbIqtSg/vqg0 J7X4EKM0B4uSOO/cXe9DhATSE0tSs1NTC1KLYLJMHJxSDYy5fFfnCh3SYFl75dzGGcGlfv26 8Uf/tuxvrusoeOB4Mm//DK2Hd/h0Xr9Q8lz7vPXh9eB7K7JmJN44s+3lVpZv2eaTZG9NWGqV O3/+Q5YXrge5Xh3e4RT5SPGqMadS1hOLw7efW/x46+nefOW+yf3Dzx8qe/8K2+jzbNqJGl7H g7/+TyifJnTXX4mlOCPRUIu5qDgRADbnN0U4AgAA Cc: Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Seung-Woo Kim , Andrzej Hajda , Tobias Jakobi , Marek Szyprowski X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP 'zpos' plane property is configurable, so adjust hardware layers priority based on the zpos value. 'zpos' value shifted by one can be used directly as hw priority value and stored to the registers, because mixer accepts priority values from 1 to 15 (0 means that layer is disabled). This patch also changes the default layer priority to match already exposed initial zpos values. The initial configuration is now: [top] video > gfx layer1 > gfx layer0 [bottom]. Signed-off-by: Marek Szyprowski --- drivers/gpu/drm/exynos/exynos_mixer.c | 39 +++++++++++++++++++---------------- drivers/gpu/drm/exynos/regs-mixer.h | 3 +++ 2 files changed, 24 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 0dceeb2b532c..c0d128bc084b 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -117,19 +117,22 @@ static const struct exynos_drm_plane_config plane_configs[MIXER_WIN_NR] = { .type = DRM_PLANE_TYPE_PRIMARY, .pixel_formats = mixer_formats, .num_pixel_formats = ARRAY_SIZE(mixer_formats), - .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE, + .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | + EXYNOS_DRM_PLANE_CAP_ZPOS, }, { .zpos = 1, .type = DRM_PLANE_TYPE_CURSOR, .pixel_formats = mixer_formats, .num_pixel_formats = ARRAY_SIZE(mixer_formats), - .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE, + .capabilities = EXYNOS_DRM_PLANE_CAP_DOUBLE | + EXYNOS_DRM_PLANE_CAP_ZPOS, }, { .zpos = 2, .type = DRM_PLANE_TYPE_OVERLAY, .pixel_formats = vp_formats, .num_pixel_formats = ARRAY_SIZE(vp_formats), - .capabilities = EXYNOS_DRM_PLANE_CAP_SCALE, + .capabilities = EXYNOS_DRM_PLANE_CAP_SCALE | + EXYNOS_DRM_PLANE_CAP_ZPOS, }, }; @@ -372,7 +375,7 @@ static void mixer_cfg_rgb_fmt(struct mixer_context *ctx, unsigned int height) } static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win, - bool enable) + unsigned int priority, bool enable) { struct mixer_resources *res = &ctx->mixer_res; u32 val = enable ? ~0 : 0; @@ -380,15 +383,24 @@ static void mixer_cfg_layer(struct mixer_context *ctx, unsigned int win, switch (win) { case 0: mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP0_ENABLE); + mixer_reg_writemask(res, MXR_LAYER_CFG, + MXR_LAYER_CFG_GRP0_VAL(priority), + MXR_LAYER_CFG_GRP0_MASK); break; case 1: mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_GRP1_ENABLE); + mixer_reg_writemask(res, MXR_LAYER_CFG, + MXR_LAYER_CFG_GRP1_VAL(priority), + MXR_LAYER_CFG_GRP1_MASK); break; case 2: if (ctx->vp_enabled) { vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON); mixer_reg_writemask(res, MXR_CFG, val, MXR_CFG_VP_ENABLE); + mixer_reg_writemask(res, MXR_LAYER_CFG, + MXR_LAYER_CFG_VP_VAL(priority), + MXR_LAYER_CFG_VP_MASK); /* control blending of graphic layer 0 */ mixer_reg_writemask(res, MXR_GRAPHIC_CFG(0), val, @@ -511,7 +523,7 @@ static void vp_video_buffer(struct mixer_context *ctx, mixer_cfg_scan(ctx, mode->vdisplay); mixer_cfg_rgb_fmt(ctx, mode->vdisplay); - mixer_cfg_layer(ctx, plane->index, true); + mixer_cfg_layer(ctx, plane->index, state->zpos + 1, true); mixer_run(ctx); mixer_vsync_set_update(ctx, true); @@ -626,7 +638,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx, mixer_cfg_scan(ctx, mode->vdisplay); mixer_cfg_rgb_fmt(ctx, mode->vdisplay); - mixer_cfg_layer(ctx, win, true); + mixer_cfg_layer(ctx, win, state->zpos + 1, true); /* layer update mandatory for mixer 16.0.33.0 */ if (ctx->mxr_ver == MXR_VER_16_0_33_0 || @@ -674,17 +686,8 @@ static void mixer_win_reset(struct mixer_context *ctx) mixer_reg_writemask(res, MXR_STATUS, MXR_STATUS_16_BURST, MXR_STATUS_BURST_MASK); - /* setting default layer priority: layer1 > layer0 > video - * because typical usage scenario would be - * layer1 - OSD - * layer0 - framebuffer - * video - video overlay - */ - val = MXR_LAYER_CFG_GRP1_VAL(3); - val |= MXR_LAYER_CFG_GRP0_VAL(2); - if (ctx->vp_enabled) - val |= MXR_LAYER_CFG_VP_VAL(1); - mixer_reg_write(res, MXR_LAYER_CFG, val); + /* reset default layer priority */ + mixer_reg_write(res, MXR_LAYER_CFG, 0); /* setting background color */ mixer_reg_write(res, MXR_BG_COLOR0, 0x008080); @@ -982,7 +985,7 @@ static void mixer_disable_plane(struct exynos_drm_crtc *crtc, spin_lock_irqsave(&res->reg_slock, flags); mixer_vsync_set_update(mixer_ctx, false); - mixer_cfg_layer(mixer_ctx, plane->index, false); + mixer_cfg_layer(mixer_ctx, plane->index, 0, false); mixer_vsync_set_update(mixer_ctx, true); spin_unlock_irqrestore(&res->reg_slock, flags); diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h index ac60260c2389..dbdbc0af3358 100644 --- a/drivers/gpu/drm/exynos/regs-mixer.h +++ b/drivers/gpu/drm/exynos/regs-mixer.h @@ -145,8 +145,11 @@ /* bit for MXR_LAYER_CFG */ #define MXR_LAYER_CFG_GRP1_VAL(x) MXR_MASK_VAL(x, 11, 8) +#define MXR_LAYER_CFG_GRP1_MASK MXR_LAYER_CFG_GRP1_VAL(~0) #define MXR_LAYER_CFG_GRP0_VAL(x) MXR_MASK_VAL(x, 7, 4) +#define MXR_LAYER_CFG_GRP0_MASK MXR_LAYER_CFG_GRP0_VAL(~0) #define MXR_LAYER_CFG_VP_VAL(x) MXR_MASK_VAL(x, 3, 0) +#define MXR_LAYER_CFG_VP_MASK MXR_LAYER_CFG_VP_VAL(~0) #endif /* SAMSUNG_REGS_MIXER_H */