From patchwork Tue Jan 12 15:15:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Zabel X-Patchwork-Id: 8018121 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DC255BEEED for ; Tue, 12 Jan 2016 15:16:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 991A4203EB for ; Tue, 12 Jan 2016 15:16:25 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 56E4620411 for ; Tue, 12 Jan 2016 15:16:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0421D6E670; Tue, 12 Jan 2016 07:16:11 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from metis.ext.4.pengutronix.de (metis.ext.4.pengutronix.de [92.198.50.35]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8CA336E673 for ; Tue, 12 Jan 2016 07:16:08 -0800 (PST) Received: from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7] helo=dude.pengutronix.de.) by metis.ext.pengutronix.de with esmtp (Exim 4.80) (envelope-from ) id 1aJ0g2-00008r-Sm; Tue, 12 Jan 2016 16:16:06 +0100 From: Philipp Zabel To: dri-devel@lists.freedesktop.org Subject: [PATCH v9 07/14] drm/mediatek: enable hdmi output control bit Date: Tue, 12 Jan 2016 16:15:43 +0100 Message-Id: <1452611750-16283-8-git-send-email-p.zabel@pengutronix.de> X-Mailer: git-send-email 2.6.4 In-Reply-To: <1452611750-16283-1-git-send-email-p.zabel@pengutronix.de> References: <1452611750-16283-1-git-send-email-p.zabel@pengutronix.de> X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::7 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: dri-devel@lists.freedesktop.org Cc: Mark Rutland , Michael Turquette , Jie Qiu , Cawa Cheng , YT Shen , Yingjoe Chen , devicetree@vger.kernel.org, Jitao Shi , kernel@pengutronix.de, Pawel Moll , Ian Campbell , Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , Paul Bolle , Stephen Boyd , Tomasz Figa , Kumar Gala X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Jie Qiu MT8173 HDMI hardware has a output control bit to enable/disable HDMI output. Because of security reason, so this bit can ONLY be controlled in ARM supervisor mode. Now the only way to enter ARM supervisor is the ARM trusted firmware. So atf provides a API for HDMI driver to call to setup this HDMI control bit to enable HDMI output in supervisor mode. Signed-off-by: Jie Qiu Signed-off-by: Philipp Zabel --- drivers/gpu/drm/mediatek/mtk_hdmi_hw.c | 11 +++++++++++ drivers/gpu/drm/mediatek/mtk_hdmi_regs.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c b/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c index 99c7ffc..054afc6 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_hw.c @@ -19,8 +19,15 @@ #include #include #include +#include #include +static int (*invoke_psci_fn)(u64, u64, u64, u64); +typedef int (*psci_initcall_t)(const struct device_node *); + +asmlinkage int __invoke_psci_fn_hvc(u64, u64, u64, u64); +asmlinkage int __invoke_psci_fn_smc(u64, u64, u64, u64); + static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset) { return readl(hdmi->regs + offset); @@ -50,6 +57,10 @@ void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable) { + invoke_psci_fn = __invoke_psci_fn_smc; + invoke_psci_fn(MTK_SIP_SET_AUTHORIZED_SECURE_REG, + 0x14000904, 0x80000000, 0); + regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20, HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0); regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C, diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h index de7ee22..8d7d60a 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_regs.h @@ -218,4 +218,5 @@ #define MHL_SYNC_AUTO_EN BIT(30) #define HDMI_PCLK_FREE_RUN BIT(31) +#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x82000001 #endif