From patchwork Mon Feb 8 02:45:24 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mike Lothian X-Patchwork-Id: 8246551 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 018DDBEEE5 for ; Mon, 8 Feb 2016 02:45:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B5404201CD for ; Mon, 8 Feb 2016 02:45:57 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 230A5201C8 for ; Mon, 8 Feb 2016 02:45:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 393E789CBA; Sun, 7 Feb 2016 18:45:54 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wm0-f41.google.com (mail-wm0-f41.google.com [74.125.82.41]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8BA6489CBA for ; Sun, 7 Feb 2016 18:45:51 -0800 (PST) Received: by mail-wm0-f41.google.com with SMTP id g62so97997989wme.0 for ; Sun, 07 Feb 2016 18:45:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fireburn-co-uk.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=lYkBEHvCZYEFg8HHdiON6c5WfE2NzMs/r9+f82ij51c=; b=ojE5zerKK9Q9M2ZTwj0SftCQ/7PGrNA306t4fo4KYbR2U8yjioz2tzPFL8CTY89VW8 PnCj7ZsfVqXKacq+nBMz+W2je9ADHCKZtX13eMAdEj79FrbC5QWmOzP5LPWXoOXOpSVA fIhvcjdqQWaNzUxi7e03cm0fgfq8qeJlnbOblfuoggH8QzWiE03syprK4iF7T6j0IA1o 8/rBGAbQ8JQHzIrciSHaW7IqVtlLLY2prBeDFZMOWM3DkJLeBksDPhF8HOso7lwPMiaK Whwl6YGMU7Qp6nQKQ7ESDugpSfKrTNCLS6hVmxVt9LjL092QdS5ucSQl/195m3bbuVVz QBew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=lYkBEHvCZYEFg8HHdiON6c5WfE2NzMs/r9+f82ij51c=; b=kEAfbis8SLPB6Vx17t/UEjL+eOFbj2bXkuuVG2e/ekAjbEVIbN2gqZn3hp1/fKN8M9 AzqDquVSihNG4/P+ticeUJLh1c+RJY+hMnAy2wyLbRr/NfN6tyM1Nl7tI8i8eCrc6peI vTLLpX58sYGTwGXbbJ9GKQNrcJg3Uj+/4cWggUmiQ5DJLNskwfJvvy3m98P5t2pj4Rkl nxrPKeEfboXJwqdVG+7sVoxunK+nkjY4wrZ7OHJUWw6yDo6vVVmuhc2sXt45q9QZNrcJ RkKtVdWkjQwhpJNkRS/1IFxz5gx15Igx7aEFbTmKLb1gRAL1IgO5jRDhT5aSjCfaeEfr mbkQ== X-Gm-Message-State: AG10YOToaDR8lBF+DFyiS8P6amHeZKAt05kPIVpgXmzyjiDwgcxmrISGzjSoc7d+vQrYvA== X-Received: by 10.28.232.194 with SMTP id f63mr30080174wmi.48.1454899549753; Sun, 07 Feb 2016 18:45:49 -0800 (PST) Received: from axion.fireburn.co.uk (158.108.198.146.dyn.plus.net. [146.198.108.158]) by smtp.gmail.com with ESMTPSA id y188sm10298033wmy.11.2016.02.07.18.45.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 07 Feb 2016 18:45:48 -0800 (PST) From: Mike Lothian To: dri-devel@lists.freedesktop.org Subject: [PATCH] drm/radeon Make CIK support optional Date: Mon, 8 Feb 2016 02:45:24 +0000 Message-Id: <1454899524-13257-1-git-send-email-mike@fireburn.co.uk> X-Mailer: git-send-email 2.7.1 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This will allow us to disable CIK support in the radeon driver, so both radeon and amdgpu can be around at the same time without conflicting Signed-of-by: Mike Lothian --- I've tested this on my Kabini system radeon doesn't initalise when compiled in but I do get these messages in my dmesg: [drm] radeon kernel modesetting enabled. [drm] initializing kernel modesetting (KABINI 0x1002:0x9832 0x1025:0x0800). radeon 0000:00:01.0: Fatal error during GPU init radeon: probe of 0000:00:01.0 failed with error -22 Am I going down the right route with this? drivers/gpu/drm/amd/amdgpu/Kconfig | 1 + drivers/gpu/drm/radeon/Kconfig | 11 +++++++++++ drivers/gpu/drm/radeon/Makefile | 11 +++++++---- drivers/gpu/drm/radeon/atombios_encoders.c | 5 +++++ drivers/gpu/drm/radeon/evergreen.c | 24 ++++++++++++++++++++++++ drivers/gpu/drm/radeon/radeon_asic.c | 13 +++++++++++++ 6 files changed, 61 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig index b30fcfa..bb58f17 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -1,6 +1,7 @@ config DRM_AMDGPU_CIK bool "Enable amdgpu support for CIK parts" depends on DRM_AMDGPU + depends on !DRM_RADEON_CIK help Choose this option if you want to enable experimental support for CIK asics. diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig index 9909f5c..32bc77e 100644 --- a/drivers/gpu/drm/radeon/Kconfig +++ b/drivers/gpu/drm/radeon/Kconfig @@ -1,3 +1,14 @@ +config DRM_RADEON_CIK + bool "Enable radeon support for CIK parts" + depends on DRM_RADEON + default y + help + Choose this option if you want to enable support for CIK + asics. + + Consider disabling this option if you wish to enable CIK + in the amdgpu driver. + config DRM_RADEON_USERPTR bool "Always enable userptr support" depends on DRM_RADEON diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile index 08bd17d..6c43901 100644 --- a/drivers/gpu/drm/radeon/Makefile +++ b/drivers/gpu/drm/radeon/Makefile @@ -72,13 +72,15 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ evergreen.o evergreen_cs.o evergreen_blit_shaders.o \ evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \ atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \ - si_blit_shaders.o radeon_prime.o cik.o cik_blit_shaders.o \ + si_blit_shaders.o radeon_prime.o \ r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \ rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \ - trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \ - ci_dpm.o dce6_afmt.o radeon_vm.o radeon_ucode.o radeon_ib.o \ + trinity_smc.o ni_dpm.o si_smc.o si_dpm.o \ + dce6_afmt.o radeon_vm.o radeon_ucode.o radeon_ib.o \ radeon_sync.o radeon_audio.o radeon_dp_auxch.o radeon_dp_mst.o +radeon-$(CONFIG_DRM_RADEON_CIK) += cik.o cik_blit_shaders.o kv_smc.o kv_dpm.o ci_smc.o ci_dpm.o + radeon-$(CONFIG_MMU_NOTIFIER) += radeon_mn.o # add async DMA block @@ -88,7 +90,8 @@ radeon-y += \ evergreen_dma.o \ ni_dma.o \ si_dma.o \ - cik_sdma.o \ + +radeon-$(CONFIG_DRM_RADEON_CIK) += cik_sdma.o # add UVD block radeon-y += \ diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c index 01b20e1..2bb81d2 100644 --- a/drivers/gpu/drm/radeon/atombios_encoders.c +++ b/drivers/gpu/drm/radeon/atombios_encoders.c @@ -2506,10 +2506,15 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder) /* this is needed for the pll/ss setup to work correctly in some cases */ atombios_set_encoder_crtc_source(encoder); /* set up the FMT blocks */ +#ifdef CONFIG_DRM_RADEON_CIK if (ASIC_IS_DCE8(rdev)) dce8_program_fmt(encoder); else if (ASIC_IS_DCE4(rdev)) dce4_program_fmt(encoder); +#else + if (ASIC_IS_DCE4(rdev)) + dce4_program_fmt(encoder); +#endif else if (ASIC_IS_DCE3(rdev)) dce3_program_fmt(encoder); else if (ASIC_IS_AVIVO(rdev)) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 2ad4628..f431946 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -209,12 +209,19 @@ extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev, int ring, u32 cp_int_cntl); extern void cayman_vm_decode_fault(struct radeon_device *rdev, u32 status, u32 addr); + +#ifdef CONFIG_DRM_RADEON_CIK void cik_init_cp_pg_table(struct radeon_device *rdev); +#endif extern u32 si_get_csb_size(struct radeon_device *rdev); extern void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer); + +#ifdef CONFIG_DRM_RADEON_CIK extern u32 cik_get_csb_size(struct radeon_device *rdev); extern void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer); +#endif + extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev); static const u32 evergreen_golden_registers[] = @@ -4160,11 +4167,17 @@ int sumo_rlc_init(struct radeon_device *rdev) if (cs_data) { /* clear state block */ +#ifdef CONFIG_DRM_RADEON_CIK if (rdev->family >= CHIP_BONAIRE) { rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev); } else if (rdev->family >= CHIP_TAHITI) { rdev->rlc.clear_state_size = si_get_csb_size(rdev); dws = rdev->rlc.clear_state_size + (256 / 4); +#else + if (rdev->family >= CHIP_TAHITI) { + rdev->rlc.clear_state_size = si_get_csb_size(rdev); + dws = rdev->rlc.clear_state_size + (256 / 4); +#endif } else { reg_list_num = 0; dws = 0; @@ -4211,6 +4224,7 @@ int sumo_rlc_init(struct radeon_device *rdev) } /* set up the cs buffer */ dst_ptr = rdev->rlc.cs_ptr; +#ifdef CONFIG_DRM_RADEON_CIK if (rdev->family >= CHIP_BONAIRE) { cik_get_csb_buffer(rdev, dst_ptr); } else if (rdev->family >= CHIP_TAHITI) { @@ -4219,6 +4233,14 @@ int sumo_rlc_init(struct radeon_device *rdev) dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size); si_get_csb_buffer(rdev, &dst_ptr[(256/4)]); +#else + if (rdev->family >= CHIP_TAHITI) { + reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256; + dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr)); + dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr)); + dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size); + si_get_csb_buffer(rdev, &dst_ptr[(256/4)]); +#endif } else { reg_list_hdr_blk_index = 0; reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4); @@ -4288,7 +4310,9 @@ int sumo_rlc_init(struct radeon_device *rdev) return r; } +#ifdef CONFIG_DRM_RADEON_CIK cik_init_cp_pg_table(rdev); +#endif radeon_bo_kunmap(rdev->rlc.cp_table_obj); radeon_bo_unreserve(rdev->rlc.cp_table_obj); diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 7d5a36d..2f4beff 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -126,6 +126,7 @@ static void radeon_register_accessor_init(struct radeon_device *rdev) rdev->mc_wreg = &rs780_mc_wreg; } +#ifdef CONFIG_DRM_RADEON_CIK if (rdev->family >= CHIP_BONAIRE) { rdev->pciep_rreg = &cik_pciep_rreg; rdev->pciep_wreg = &cik_pciep_wreg; @@ -133,6 +134,12 @@ static void radeon_register_accessor_init(struct radeon_device *rdev) rdev->pciep_rreg = &r600_pciep_rreg; rdev->pciep_wreg = &r600_pciep_wreg; } +#else + if (rdev->family >= CHIP_R600) { + rdev->pciep_rreg = &r600_pciep_rreg; + rdev->pciep_wreg = &r600_pciep_wreg; + } +#endif } static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev, @@ -2023,6 +2030,8 @@ static struct radeon_asic si_asic = { }, }; +#ifdef CONFIG_DRM_RADEON_CIK + static const struct radeon_asic_ring ci_gfx_ring = { .ib_execute = &cik_ring_ib_execute, .ib_parse = &cik_ib_parse, @@ -2303,6 +2312,8 @@ static struct radeon_asic kv_asic = { }, }; +#endif + /** * radeon_asic_init - register asic specific callbacks * @@ -2573,6 +2584,7 @@ int radeon_asic_init(struct radeon_device *rdev) break; } break; +#ifdef CONFIG_DRM_RADEON_CIK case CHIP_BONAIRE: case CHIP_HAWAII: rdev->asic = &ci_asic; @@ -2679,6 +2691,7 @@ int radeon_asic_init(struct radeon_device *rdev) } rdev->has_uvd = true; break; +#endif default: /* FIXME: not supported yet */ return -EINVAL;