diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig
index b30fcfa..bb58f17 100644
--- a/drivers/gpu/drm/amd/amdgpu/Kconfig
+++ b/drivers/gpu/drm/amd/amdgpu/Kconfig
@@ -1,6 +1,7 @@
 config DRM_AMDGPU_CIK
 	bool "Enable amdgpu support for CIK parts"
 	depends on DRM_AMDGPU
+	depends on !DRM_RADEON_CIK
 	help
 	  Choose this option if you want to enable experimental support
 	  for CIK asics.
diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig
index 9909f5c..32bc77e 100644
--- a/drivers/gpu/drm/radeon/Kconfig
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -1,3 +1,14 @@
+config DRM_RADEON_CIK
+	bool "Enable radeon support for CIK parts"
+	depends on DRM_RADEON
+	default y
+	help
+	  Choose this option if you want to enable support for CIK
+	  asics.
+
+	  Consider disabling this option if you wish to enable CIK
+	  in the amdgpu driver.
+
 config DRM_RADEON_USERPTR
 	bool "Always enable userptr support"
 	depends on DRM_RADEON
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 08bd17d..6c43901 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -72,13 +72,15 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
 	evergreen.o evergreen_cs.o evergreen_blit_shaders.o \
 	evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
 	atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
-	si_blit_shaders.o radeon_prime.o cik.o cik_blit_shaders.o \
+	si_blit_shaders.o radeon_prime.o \
 	r600_dpm.o rs780_dpm.o rv6xx_dpm.o rv770_dpm.o rv730_dpm.o rv740_dpm.o \
 	rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \
-	trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \
-	ci_dpm.o dce6_afmt.o radeon_vm.o radeon_ucode.o radeon_ib.o \
+	trinity_smc.o ni_dpm.o si_smc.o si_dpm.o \
+	dce6_afmt.o radeon_vm.o radeon_ucode.o radeon_ib.o \
 	radeon_sync.o radeon_audio.o radeon_dp_auxch.o radeon_dp_mst.o
 
+radeon-$(CONFIG_DRM_RADEON_CIK) += cik.o cik_blit_shaders.o kv_smc.o kv_dpm.o ci_smc.o ci_dpm.o
+
 radeon-$(CONFIG_MMU_NOTIFIER) += radeon_mn.o
 
 # add async DMA block
@@ -88,7 +90,8 @@ radeon-y += \
 	evergreen_dma.o \
 	ni_dma.o \
 	si_dma.o \
-	cik_sdma.o \
+
+radeon-$(CONFIG_DRM_RADEON_CIK) += cik_sdma.o
 
 # add UVD block
 radeon-y += \
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 01b20e1..2bb81d2 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -2506,10 +2506,15 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
 	/* this is needed for the pll/ss setup to work correctly in some cases */
 	atombios_set_encoder_crtc_source(encoder);
 	/* set up the FMT blocks */
+#ifdef CONFIG_DRM_RADEON_CIK
 	if (ASIC_IS_DCE8(rdev))
 		dce8_program_fmt(encoder);
 	else if (ASIC_IS_DCE4(rdev))
 		dce4_program_fmt(encoder);
+#else
+	if (ASIC_IS_DCE4(rdev))
+		dce4_program_fmt(encoder);
+#endif
 	else if (ASIC_IS_DCE3(rdev))
 		dce3_program_fmt(encoder);
 	else if (ASIC_IS_AVIVO(rdev))
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 2ad4628..f431946 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -209,12 +209,19 @@ extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
 				     int ring, u32 cp_int_cntl);
 extern void cayman_vm_decode_fault(struct radeon_device *rdev,
 				   u32 status, u32 addr);
+
+#ifdef CONFIG_DRM_RADEON_CIK
 void cik_init_cp_pg_table(struct radeon_device *rdev);
+#endif
 
 extern u32 si_get_csb_size(struct radeon_device *rdev);
 extern void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);
+
+#ifdef CONFIG_DRM_RADEON_CIK
 extern u32 cik_get_csb_size(struct radeon_device *rdev);
 extern void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);
+#endif
+
 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
 
 static const u32 evergreen_golden_registers[] =
@@ -4160,11 +4167,17 @@ int sumo_rlc_init(struct radeon_device *rdev)
 
 	if (cs_data) {
 		/* clear state block */
+#ifdef CONFIG_DRM_RADEON_CIK
 		if (rdev->family >= CHIP_BONAIRE) {
 			rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev);
 		} else if (rdev->family >= CHIP_TAHITI) {
 			rdev->rlc.clear_state_size = si_get_csb_size(rdev);
 			dws = rdev->rlc.clear_state_size + (256 / 4);
+#else
+		if (rdev->family >= CHIP_TAHITI) {
+			rdev->rlc.clear_state_size = si_get_csb_size(rdev);
+			dws = rdev->rlc.clear_state_size + (256 / 4);
+#endif
 		} else {
 			reg_list_num = 0;
 			dws = 0;
@@ -4211,6 +4224,7 @@ int sumo_rlc_init(struct radeon_device *rdev)
 		}
 		/* set up the cs buffer */
 		dst_ptr = rdev->rlc.cs_ptr;
+#ifdef CONFIG_DRM_RADEON_CIK
 		if (rdev->family >= CHIP_BONAIRE) {
 			cik_get_csb_buffer(rdev, dst_ptr);
 		} else if (rdev->family >= CHIP_TAHITI) {
@@ -4219,6 +4233,14 @@ int sumo_rlc_init(struct radeon_device *rdev)
 			dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
 			dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size);
 			si_get_csb_buffer(rdev, &dst_ptr[(256/4)]);
+#else
+		if (rdev->family >= CHIP_TAHITI) {
+		        reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256;
+			dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
+			dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
+			dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size);
+			si_get_csb_buffer(rdev, &dst_ptr[(256/4)]);
+#endif
 		} else {
 			reg_list_hdr_blk_index = 0;
 			reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4);
@@ -4288,7 +4310,9 @@ int sumo_rlc_init(struct radeon_device *rdev)
 			return r;
 		}
 
+#ifdef CONFIG_DRM_RADEON_CIK
 		cik_init_cp_pg_table(rdev);
+#endif
 
 		radeon_bo_kunmap(rdev->rlc.cp_table_obj);
 		radeon_bo_unreserve(rdev->rlc.cp_table_obj);
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 7d5a36d..2f4beff 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -126,6 +126,7 @@ static void radeon_register_accessor_init(struct radeon_device *rdev)
 		rdev->mc_wreg = &rs780_mc_wreg;
 	}
 
+#ifdef CONFIG_DRM_RADEON_CIK
 	if (rdev->family >= CHIP_BONAIRE) {
 		rdev->pciep_rreg = &cik_pciep_rreg;
 		rdev->pciep_wreg = &cik_pciep_wreg;
@@ -133,6 +134,12 @@ static void radeon_register_accessor_init(struct radeon_device *rdev)
 		rdev->pciep_rreg = &r600_pciep_rreg;
 		rdev->pciep_wreg = &r600_pciep_wreg;
 	}
+#else
+	if (rdev->family >= CHIP_R600) {
+		rdev->pciep_rreg = &r600_pciep_rreg;
+		rdev->pciep_wreg = &r600_pciep_wreg;
+	}
+#endif
 }
 
 static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev,
@@ -2023,6 +2030,8 @@ static struct radeon_asic si_asic = {
 	},
 };
 
+#ifdef CONFIG_DRM_RADEON_CIK
+
 static const struct radeon_asic_ring ci_gfx_ring = {
 	.ib_execute = &cik_ring_ib_execute,
 	.ib_parse = &cik_ib_parse,
@@ -2303,6 +2312,8 @@ static struct radeon_asic kv_asic = {
 	},
 };
 
+#endif
+
 /**
  * radeon_asic_init - register asic specific callbacks
  *
@@ -2573,6 +2584,7 @@ int radeon_asic_init(struct radeon_device *rdev)
 			break;
 		}
 		break;
+#ifdef CONFIG_DRM_RADEON_CIK
 	case CHIP_BONAIRE:
 	case CHIP_HAWAII:
 		rdev->asic = &ci_asic;
@@ -2679,6 +2691,7 @@ int radeon_asic_init(struct radeon_device *rdev)
 		}
 		rdev->has_uvd = true;
 		break;
+#endif
 	default:
 		/* FIXME: not supported yet */
 		return -EINVAL;
