From patchwork Fri Feb 19 00:50:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: C Stout X-Patchwork-Id: 8358371 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 93D349F88A for ; Fri, 19 Feb 2016 08:51:46 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 878912041F for ; Fri, 19 Feb 2016 08:51:45 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id EFD3D203E9 for ; Fri, 19 Feb 2016 08:51:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BCFD76EE24; Fri, 19 Feb 2016 08:51:39 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pa0-x22a.google.com (mail-pa0-x22a.google.com [IPv6:2607:f8b0:400e:c03::22a]) by gabe.freedesktop.org (Postfix) with ESMTPS id E1FB46E384 for ; Fri, 19 Feb 2016 00:52:39 +0000 (UTC) Received: by mail-pa0-x22a.google.com with SMTP id fy10so40161734pac.1 for ; Thu, 18 Feb 2016 16:52:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iURuhIobgpfVxWVpkXg+swQF0aUmZRqGXVoLWaFyhIM=; b=VuXy3pCW0EVUglv3fPAk5wCEPcxFuPPJkNUmxWbo/6Csi2JFNW82UiStd6BRQ1JthL +o9iEObHBNF8WxiX6P3o7+z+qmUaJOVnMNRyKoRu4mJeCaEpsY6DjyiOmr9E6Hp+L6Z0 Z6U1CZNmSeImCtk7XdE+4S66QwLcv5QvNhYbM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iURuhIobgpfVxWVpkXg+swQF0aUmZRqGXVoLWaFyhIM=; b=Nfpyzm/5MaKvWwlHxPPkvkZUzWKaxh0kl0jdsy9eUy2Sd7N9iKEwNMotvroHBgI+fn 3/df9xsT9QIRJhn+IjSSRbtJA9R0LGv2i2MTUlx6lJYAV0RJgktDH7YISQZe1+7b07fA QSNsG0SXbjqdWQJeSHAbc3jKS61+RCCUoicHePKxMRNdaaEOuOkHIo/3+igaYqC/KbVk KIRRUjMXnn1qrwuwNtsbIuAyE5FHYB/h9aNNOkoe4rbPOS3omnNLu4YihNnrAs4XuxFo P+Ax65kR3fV8ns7exd/AIxNTZYHuuIB+UYM8h/fakAI/5ON+NMPjQ7H5hVQiCorYMTVv rUWA== X-Gm-Message-State: AG10YORoC5n/qQYLuxhXk2Y+GHLVwRFeYRgKW+IwJJEcD2167a6G3K0/55FO2Y2HF0MUg3RV X-Received: by 10.66.141.142 with SMTP id ro14mr14222598pab.112.1455843159491; Thu, 18 Feb 2016 16:52:39 -0800 (PST) Received: from localhost.localdomain ([172.31.155.120]) by smtp.gmail.com with ESMTPSA id x1sm13038468pfi.42.2016.02.18.16.52.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 18 Feb 2016 16:52:39 -0800 (PST) From: C Stout To: dri-devel@lists.freedesktop.org Subject: [PATCH 3/4] Get CP_RPTR from register instead of shadow memory Date: Thu, 18 Feb 2016 16:50:02 -0800 Message-Id: <1455843003-60379-3-git-send-email-cstout@chromium.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1455843003-60379-1-git-send-email-cstout@chromium.org> References: <1455843003-60379-1-git-send-email-cstout@chromium.org> X-Mailman-Approved-At: Fri, 19 Feb 2016 08:51:39 +0000 Cc: cstout X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: cstout As described in the downstream/kgsl driver: Sometimes the RPTR shadow memory is unreliable causing timeouts in adreno_idle(). Read it directly from the register instead. Change-Id: I1617a670e1da0ae25528c37f3424654d5bedd169 --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 34 +++++++++++++++++++++------------ 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 0e76a21..95e582e 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -68,18 +68,15 @@ int adreno_hw_init(struct msm_gpu *gpu) adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL, /* size is log2(quad-words): */ AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) | - AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8))); + AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) | + (adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0)); /* Setup ringbuffer address: */ adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova); - adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, - rbmemptr(adreno_gpu, rptr)); - /* Setup scratch/timestamp: */ - adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_ADDR, - rbmemptr(adreno_gpu, fence)); - - adreno_gpu_write(adreno_gpu, REG_ADRENO_SCRATCH_UMSK, 0x1); + if (!adreno_is_a430(adreno_gpu)) + adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR, + rbmemptr(adreno_gpu, rptr)); return 0; } @@ -89,6 +86,16 @@ static uint32_t get_wptr(struct msm_ringbuffer *ring) return ring->cur - ring->start; } +/* Use this helper to read rptr, since a430 doesn't update rptr in memory */ +static uint32_t get_rptr(struct adreno_gpu *adreno_gpu) +{ + if (adreno_is_a430(adreno_gpu)) + return adreno_gpu->memptrs->rptr = adreno_gpu_read( + adreno_gpu, REG_ADRENO_CP_RB_RPTR); + else + return adreno_gpu->memptrs->rptr; +} + uint32_t adreno_last_fence(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -217,9 +224,12 @@ void adreno_idle(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); uint32_t wptr = get_wptr(gpu->rb); + int ret; /* wait for CP to drain ringbuffer: */ - if (spin_until(adreno_gpu->memptrs->rptr == wptr)) + ret = spin_until(get_rptr(adreno_gpu) == wptr); + + if (ret) DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name); /* TODO maybe we need to reset GPU here to recover from hang? */ @@ -238,7 +248,7 @@ void adreno_show(struct msm_gpu *gpu, struct seq_file *m) seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence, gpu->submitted_fence); - seq_printf(m, "rptr: %d\n", adreno_gpu->memptrs->rptr); + seq_printf(m, "rptr: %d\n", get_rptr(adreno_gpu)); seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr); seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb)); @@ -279,7 +289,7 @@ void adreno_dump_info(struct msm_gpu *gpu) printk("fence: %d/%d\n", adreno_gpu->memptrs->fence, gpu->submitted_fence); - printk("rptr: %d\n", adreno_gpu->memptrs->rptr); + printk("rptr: %d\n", get_rptr(adreno_gpu)); printk("wptr: %d\n", adreno_gpu->memptrs->wptr); printk("rb wptr: %d\n", get_wptr(gpu->rb)); @@ -314,7 +324,7 @@ static uint32_t ring_freewords(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); uint32_t size = gpu->rb->size / 4; uint32_t wptr = get_wptr(gpu->rb); - uint32_t rptr = adreno_gpu->memptrs->rptr; + uint32_t rptr = get_rptr(adreno_gpu); return (rptr + (size - 1) - wptr) % size; }