From patchwork Fri Feb 19 09:47:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 8358911 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1D5279F88A for ; Fri, 19 Feb 2016 09:49:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C9AE72042B for ; Fri, 19 Feb 2016 09:49:28 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E20C620429 for ; Fri, 19 Feb 2016 09:49:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 48E236EE8B; Fri, 19 Feb 2016 09:49:20 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5A27E6EE70 for ; Fri, 19 Feb 2016 09:49:03 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id u1J9n16V016181; Fri, 19 Feb 2016 03:49:01 -0600 Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u1J9n1I1007547; Fri, 19 Feb 2016 03:49:01 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Fri, 19 Feb 2016 03:49:00 -0600 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u1J9mP7Q023949; Fri, 19 Feb 2016 03:48:59 -0600 From: Tomi Valkeinen To: , Laurent Pinchart Subject: [PATCH 22/33] drm/omap: HDMI: Fix HSW value Date: Fri, 19 Feb 2016 11:47:57 +0200 Message-ID: <1455875288-4370-23-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1455875288-4370-1-git-send-email-tomi.valkeinen@ti.com> References: <1455875288-4370-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Cc: Tomi Valkeinen X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On OMAP4 and OMAP5 ES1.0 the HDMI_WP_VIDEO_TIMING_H:HSW field is set directly to the HSW value. On later SoCs the field needs to be programmed with the value of HSW-1. Currently the driver always programs the field with the HSW value. Most videomodes seem to work fine with that, but at least low resolution interlaced modes don't work at all. This patch fixes the HSW for OMAP5 ES2.0+ SoCs. Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/hdmi_wp.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c index 7c544bc56fb5..48ffb39663c8 100644 --- a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c +++ b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c @@ -165,12 +165,24 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, { u32 timing_h = 0; u32 timing_v = 0; + bool hsw_minus_one = true; DSSDBG("Enter hdmi_wp_video_config_timing\n"); + /* + * On OMAP4 and OMAP5 ES1 the HSW field is programmed as is. On OMAP5 + * ES2+ (including DRA7/AM5 SoCs) HSW field is programmed to hsw-1. + * However, we don't support OMAP5 ES1 at all, so we can just check for + * OMAP4 here. + */ + if (omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES1 || + omapdss_get_version() == OMAPDSS_VER_OMAP4430_ES2 || + omapdss_get_version() == OMAPDSS_VER_OMAP4) + hsw_minus_one = false; + timing_h |= FLD_VAL(timings->hbp, 31, 20); timing_h |= FLD_VAL(timings->hfp, 19, 8); - timing_h |= FLD_VAL(timings->hsw, 7, 0); + timing_h |= FLD_VAL(timings->hsw - (hsw_minus_one ? 1 : 0), 7, 0); hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h); timing_v |= FLD_VAL(timings->vbp, 31, 20);