From patchwork Fri Mar 18 18:08:56 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tiago Vignatti X-Patchwork-Id: 8622791 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 16EF4C0553 for ; Fri, 18 Mar 2016 18:09:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 172822034A for ; Fri, 18 Mar 2016 18:09:14 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 0380420303 for ; Fri, 18 Mar 2016 18:09:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 032F96E134; Fri, 18 Mar 2016 18:09:08 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id E28BB6E134; Fri, 18 Mar 2016 18:09:05 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP; 18 Mar 2016 11:09:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,356,1455004800"; d="scan'208";a="914118818" Received: from tvignatt-mobl3.amr.corp.intel.com ([10.254.74.232]) by orsmga001.jf.intel.com with ESMTP; 18 Mar 2016 11:09:04 -0700 From: Tiago Vignatti To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v3] prime_mmap_coherency: Add return error tests for prime sync ioctl Date: Fri, 18 Mar 2016 15:08:56 -0300 Message-Id: <1458324536-4550-1-git-send-email-tiago.vignatti@intel.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <20160318094440.GB21717@nuc-i3427.alporthouse.com> References: <20160318094440.GB21717@nuc-i3427.alporthouse.com> Cc: daniel.vetter@ffwll.ch X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds ioctl-errors subtest to be used for exercising prime sync ioctl errors. The subtest constantly interrupts via signals a function doing concurrent blit to stress out the right usage of prime_sync_*, making sure these ioctl errors are handled accordingly. Important to note that in case of failure (e.g. in a case where the ioctl wouldn't try again in a return error) this test does not reliably catch the problem with 100% of accuracy. v2: fix prime sync direction when reading mmap'ed file. v3: change the upper bound using time rather than loops Cc: Chris Wilson Signed-off-by: Tiago Vignatti --- tests/prime_mmap_coherency.c | 89 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/tests/prime_mmap_coherency.c b/tests/prime_mmap_coherency.c index 180d8a4..d2b2a4f 100644 --- a/tests/prime_mmap_coherency.c +++ b/tests/prime_mmap_coherency.c @@ -180,6 +180,90 @@ static void test_write_flush(bool expect_stale_cache) munmap(ptr_cpu, width * height); } +static void blit_and_cmp(void) +{ + drm_intel_bo *bo_1; + drm_intel_bo *bo_2; + uint32_t *ptr_cpu; + uint32_t *ptr2_cpu; + int dma_buf_fd, dma_buf2_fd, i; + int local_fd; + drm_intel_bufmgr *local_bufmgr; + struct intel_batchbuffer *local_batch; + + /* recreate process local variables */ + local_fd = drm_open_driver(DRIVER_INTEL); + local_bufmgr = drm_intel_bufmgr_gem_init(local_fd, 4096); + igt_assert(local_bufmgr); + + local_batch = intel_batchbuffer_alloc(local_bufmgr, intel_get_drm_devid(local_fd)); + igt_assert(local_batch); + + bo_1 = drm_intel_bo_alloc(local_bufmgr, "BO 1", width * height * 4, 4096); + dma_buf_fd = prime_handle_to_fd_for_mmap(local_fd, bo_1->handle); + igt_skip_on(errno == EINVAL); + + ptr_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE, + MAP_SHARED, dma_buf_fd, 0); + igt_assert(ptr_cpu != MAP_FAILED); + + bo_2 = drm_intel_bo_alloc(local_bufmgr, "BO 2", width * height * 4, 4096); + dma_buf2_fd = prime_handle_to_fd_for_mmap(local_fd, bo_2->handle); + + ptr2_cpu = mmap(NULL, width * height, PROT_READ | PROT_WRITE, + MAP_SHARED, dma_buf2_fd, 0); + igt_assert(ptr2_cpu != MAP_FAILED); + + /* Fill up BO 1 with '1's and BO 2 with '0's */ + prime_sync_start(dma_buf_fd, true); + memset(ptr_cpu, 0x11, width * height); + prime_sync_end(dma_buf_fd, true); + + prime_sync_start(dma_buf2_fd, true); + memset(ptr2_cpu, 0x00, width * height); + prime_sync_end(dma_buf2_fd, true); + + /* Copy BO 1 into BO 2, using blitter. */ + intel_copy_bo(local_batch, bo_2, bo_1, width * height); + usleep(0); /* let someone else claim the mutex */ + + /* Compare BOs. If prime_sync_* were executed properly, the caches + * should be synced. */ + prime_sync_start(dma_buf2_fd, false); + for (i = 0; i < (width * height) / 4; i++) + igt_fail_on_f(ptr2_cpu[i] != 0x11111111, "Found 0x%08x at offset 0x%08x\n", ptr2_cpu[i], i); + prime_sync_end(dma_buf2_fd, false); + + drm_intel_bo_unreference(bo_1); + drm_intel_bo_unreference(bo_2); + munmap(ptr_cpu, width * height); + munmap(ptr2_cpu, width * height); +} + +/* + * Constantly interrupt concurrent blits to stress out prime_sync_* and make + * sure these ioctl errors are handled accordingly. + * + * Important to note that in case of failure (e.g. in a case where the ioctl + * wouldn't try again in a return error) this test does not reliably catch the + * problem with 100% of accuracy. + */ +static void test_ioctl_errors(void) +{ + int ncpus = sysconf(_SC_NPROCESSORS_ONLN); + + igt_fork_signal_helper(); + for (int num_children = 1; num_children <= 8 *ncpus; num_children <<= 1) { + igt_fork(child, num_children) { + struct timespec start = {}; + while (igt_nsec_elapsed(&start) <= num_children) + blit_and_cmp(); + } + igt_waitchildren(); + } + igt_stop_signal_helper(); +} + int main(int argc, char **argv) { int i; @@ -235,6 +319,11 @@ int main(int argc, char **argv) igt_fail_on_f(!stale, "couldn't find any stale cache lines\n"); } + igt_subtest("ioctl-errors") { + igt_info("exercising concurrent blit to get ioctl errors\n"); + test_ioctl_errors(); + } + igt_fixture { intel_batchbuffer_free(batch); drm_intel_bufmgr_destroy(bufmgr);