From patchwork Tue Apr 5 08:27:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inki Dae X-Patchwork-Id: 8748731 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A4A9AC0554 for ; Tue, 5 Apr 2016 08:27:54 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 84AAD202BE for ; Tue, 5 Apr 2016 08:27:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id E5C152034F for ; Tue, 5 Apr 2016 08:27:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F1EB36E704; Tue, 5 Apr 2016 08:27:50 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8DD126E702 for ; Tue, 5 Apr 2016 08:27:49 +0000 (UTC) Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O5501WZBJIBNI60@mailout3.samsung.com> for dri-devel@lists.freedesktop.org; Tue, 05 Apr 2016 17:27:47 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.114]) by epcpsbgr2.samsung.com (EPCPMTA) with SMTP id 3D.42.04785.30773075; Tue, 5 Apr 2016 17:27:47 +0900 (KST) X-AuditID: cbfee68e-f79d96d0000012b1-1b-570377034c21 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 9A.E6.06699.30773075; Tue, 5 Apr 2016 17:27:47 +0900 (KST) Received: from localhost.localdomain ([10.113.62.206]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O55005VWJI91D20@mmp2.samsung.com>; Tue, 05 Apr 2016 17:27:46 +0900 (KST) From: Inki Dae To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/3] drm/exynos: fimd: add HW trigger support Date: Tue, 05 Apr 2016 17:27:43 +0900 Message-id: <1459844864-12065-3-git-send-email-inki.dae@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1459844864-12065-1-git-send-email-inki.dae@samsung.com> References: <1459844864-12065-1-git-send-email-inki.dae@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrOLMWRmVeSWpSXmKPExsWyRsSkSJe5nDnc4PQccYvecyeZLK58fc9m Men+BBaLGef3MTmweGz/9oDV4373cSaPvi2rGD0+b5ILYInisklJzcksSy3St0vgymi5k1sw RbOiYeM7xgbGNYpdjJwcEgImEr2dPewQtpjEhXvr2boYuTiEBFYwSpz585cRpujn5xlMEIlZ jBKfl85jhnB+MEqc+rMIrJ1NQFVi4or7bCC2iICyxN+Jq8C6mQWiJJYfXgpWIyxgK/Fq3VcW EJsFqL7v8QpWEJtXwEVi9//tUGfISZw8NhkszingKtF2bDbYHCGgmu4LKxhBFksI/GeTeDOv GWqQgMS3yYeAbA6ghKzEpgPMEHMkJQ6uuMEygVF4ASPDKkbR1ILkguKk9CIjveLE3OLSvHS9 5PzcTYzA8D3971nfDsabB6wPMQpwMCrx8M54zxQuxJpYVlyZe4jRFGjDRGYp0eR8YJTklcQb GpsZWZiamBobmVuaKYnzJkj9DBYSSE8sSc1OTS1ILYovKs1JLT7EyMTBKdXAyLogRfwu42o5 2SueaqyX3fW3Pdc1nvtIaa7fjZZLdz+/W9jX80yv87jC2fWct3/kuSy54mez/e7l5zdfvt2c HjlXYR87m2ETp4eO1R2xRJYkl/hdDzulv8/+uTK+8EnYjDbxdcmrhEwmb+fS8XiimTDV413L 1fWWj9vvZ3zRmmvV9X71VpUPYUosxRmJhlrMRcWJAJ4gWeZaAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprCIsWRmVeSWpSXmKPExsVy+t9jQV3mcuZwg8+ThCx6z51ksrjy9T2b xaT7E1gsZpzfx+TA4rH92wNWj/vdx5k8+rasYvT4vEkugCWqgdEmIzUxJbVIITUvOT8lMy/d Vsk7ON453tTMwFDX0NLCXEkhLzE31VbJxSdA1y0zB2inkkJZYk4pUCggsbhYSd8O04TQEDdd C5jGCF3fkCC4HiMDNJCwhjGj5U5uwRTNioaN7xgbGNcodjFyckgImEj8/DyDCcIWk7hwbz1b FyMXh5DALEaJz0vnMUM4PxglTv1ZxA5SxSagKjFxxX02EFtEQFni78RVjCA2s0CUxPLDS8Fq hAVsJV6t+8oCYrMA1fc9XsEKYvMKuEjs/r+dHWKbnMTJY5PB4pwCrhJtx2aDzRECqum+sIJx AiPvAkaGVYwSqQXJBcVJ6blGeanlesWJucWleel6yfm5mxjBMfJMegfj4V3uhxgFOBiVeHhn vGcKF2JNLCuuzD3EKMHBrCTCu6qYOVyINyWxsiq1KD++qDQntfgQoynQYROZpUST84Hxm1cS b2hsYmZkaWRuaGFkbK4kzvv4/7owIYH0xJLU7NTUgtQimD4mDk6pBsYjUw87dM5TPtqiNf2R z+wc8cbbsptjH33bs2L3pryw+OW3FH66aoquOmx9Z0fAd83bsxfO6Zxlt032eoa4pdybi96d CxL+drtIXpn0ovndR+H381pbhStzlsWXiog3GznKM6n1apw0vXXr5ZeGFTZCk96le/If3/nw f4rv9Jf3p3Dvj5P622qsxFKckWioxVxUnAgAI1Zr4KcCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: linux-samsung-soc@vger.kernel.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds HW trigger support on i80 mode. Until now, Exynos DRM only supported SW trigger which was set SWTRGCMD bit of TRIGCON register by CPU to transfer scanout buffer to Display bus device or panel. With this patch, the transmission to Display bus device or panel will be initiated by FIMD controller. Signed-off-by: Inki Dae --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 47 ++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 752c6b0..c4cd16a 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -72,6 +72,11 @@ #define TRIGCON 0x1A4 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0) #define SWTRGCMD_I80_RGB_ENABLE (1 << 1) +/* Exynos3250, 3472, 4415, 5260 5410, 5420 and 5422 only supported. */ +#define HWTRGEN_I80_RGB_ENABLE (1 << 3) +#define HWTRGMASK_I80_RGB_ENABLE (1 << 4) +/* Exynos3250, 3472, 4415, 5260, 5420 and 5422 only supported. */ +#define HWTRIGEN_PER_RGB_ENABLE (1 << 31) /* display mode change control register except exynos4 */ #define VIDOUT_CON 0x000 @@ -89,12 +94,16 @@ /* FIMD has totally five hardware windows. */ #define WINDOWS_NR 5 +/* HW trigger flag on i80 panel. */ +#define I80_HW_TRG (1 << 1) + struct fimd_driver_data { unsigned int timing_base; unsigned int lcdblk_offset; unsigned int lcdblk_vt_shift; unsigned int lcdblk_bypass_shift; unsigned int lcdblk_mic_bypass_shift; + unsigned int trg_type; unsigned int has_shadowcon:1; unsigned int has_clksel:1; @@ -102,6 +111,8 @@ struct fimd_driver_data { unsigned int has_vidoutcon:1; unsigned int has_vtsel:1; unsigned int has_mic_bypass:1; + unsigned int has_hw_trigger:1; + unsigned int has_trigger_per_te:1; }; static struct fimd_driver_data s3c64xx_fimd_driver_data = { @@ -114,8 +125,10 @@ static struct fimd_driver_data exynos3_fimd_driver_data = { .timing_base = 0x20000, .lcdblk_offset = 0x210, .lcdblk_bypass_shift = 1, + .trg_type = I80_HW_TRG, .has_shadowcon = 1, .has_vidoutcon = 1, + .has_trigger_per_te = 1, }; static struct fimd_driver_data exynos4_fimd_driver_data = { @@ -132,9 +145,11 @@ static struct fimd_driver_data exynos4415_fimd_driver_data = { .lcdblk_offset = 0x210, .lcdblk_vt_shift = 10, .lcdblk_bypass_shift = 1, + .trg_type = I80_HW_TRG, .has_shadowcon = 1, .has_vidoutcon = 1, .has_vtsel = 1, + .has_trigger_per_te = 1, }; static struct fimd_driver_data exynos5_fimd_driver_data = { @@ -145,6 +160,7 @@ static struct fimd_driver_data exynos5_fimd_driver_data = { .has_shadowcon = 1, .has_vidoutcon = 1, .has_vtsel = 1, + .has_hw_trigger = 1, }; static struct fimd_driver_data exynos5420_fimd_driver_data = { @@ -153,10 +169,13 @@ static struct fimd_driver_data exynos5420_fimd_driver_data = { .lcdblk_vt_shift = 24, .lcdblk_bypass_shift = 15, .lcdblk_mic_bypass_shift = 11, + .trg_type = I80_HW_TRG, .has_shadowcon = 1, .has_vidoutcon = 1, .has_vtsel = 1, .has_mic_bypass = 1, + .has_hw_trigger = 1, + .has_trigger_per_te = 1, }; struct fimd_context { @@ -400,6 +419,27 @@ static u32 fimd_calc_clkdiv(struct fimd_context *ctx, return (clkdiv < 0x100) ? clkdiv : 0xff; } +static void fimd_setup_trigger(struct fimd_context *ctx) +{ + void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base; + u32 trg_type = ctx->driver_data->trg_type; + u32 val = readl(timing_base + TRIGCON); + + val &= ~(TRGMODE_I80_RGB_ENABLE_I80); + + if (trg_type == I80_HW_TRG) { + if (ctx->driver_data->has_hw_trigger) + val |= HWTRGEN_I80_RGB_ENABLE | + HWTRGMASK_I80_RGB_ENABLE; + if (ctx->driver_data->has_trigger_per_te) + val |= HWTRIGEN_PER_RGB_ENABLE; + } else { + val |= TRGMODE_I80_RGB_ENABLE_I80; + } + + writel(val, timing_base + TRIGCON); +} + static void fimd_commit(struct exynos_drm_crtc *crtc) { struct fimd_context *ctx = crtc->ctx; @@ -495,6 +535,8 @@ static void fimd_commit(struct exynos_drm_crtc *crtc) VIDTCON2_HOZVAL_E(mode->hdisplay - 1); writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); + fimd_setup_trigger(ctx); + /* * fields of register with prefix '_F' would be updated * at vsync(same as dma start) @@ -856,11 +898,15 @@ static void fimd_trigger(struct device *dev) static void fimd_te_handler(struct exynos_drm_crtc *crtc) { struct fimd_context *ctx = crtc->ctx; + u32 trg_type = ctx->driver_data->trg_type; /* Checks the crtc is detached already from encoder */ if (ctx->pipe < 0 || !ctx->drm_dev) return; + if (trg_type == I80_HW_TRG) + goto out; + /* * If there is a page flip request, triggers and handles the page flip * event so that current fb can be updated into panel GRAM. @@ -868,6 +914,7 @@ static void fimd_te_handler(struct exynos_drm_crtc *crtc) if (atomic_add_unless(&ctx->win_updated, -1, 0)) fimd_trigger(ctx->dev); +out: /* Wakes up vsync event queue */ if (atomic_read(&ctx->wait_vsync_event)) { atomic_set(&ctx->wait_vsync_event, 0);