From patchwork Fri Apr 29 09:29:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kulkarni, Vandita" X-Patchwork-Id: 8986101 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id AB613BF29F for ; Sat, 30 Apr 2016 01:18:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AD6DD201ED for ; Sat, 30 Apr 2016 01:18:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id B3CDC201CE for ; Sat, 30 Apr 2016 01:18:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F385D6F005; Sat, 30 Apr 2016 01:18:21 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 183E16EE89; Fri, 29 Apr 2016 09:29:38 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP; 29 Apr 2016 02:29:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,551,1455004800"; d="scan'208";a="794896353" Received: from vandita-desktop.iind.intel.com ([10.223.26.11]) by orsmga003.jf.intel.com with ESMTP; 29 Apr 2016 02:29:36 -0700 From: Vandita Kulkarni To: intel-gfx@lists.freedesktop.org Subject: [PATCHv2 5/5] drm/i915/skl: Add support for blending modes Date: Fri, 29 Apr 2016 14:59:17 +0530 Message-Id: <1461922157-32553-6-git-send-email-vandita.kulkarni@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1461922157-32553-1-git-send-email-vandita.kulkarni@intel.com> References: <1461922157-32553-1-git-send-email-vandita.kulkarni@intel.com> X-Mailman-Approved-At: Sat, 30 Apr 2016 01:16:05 +0000 Cc: corbet@lwn.net, vandita kulkarni , dri-devel@lists.freedesktop.org, daniel.vetter@intel.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Damien Lespiau This patch adds support for blending modes involving color. V2: Add support for primary plane. Separate out plane alpha disable functionality from per pixel drop_alpha blend function and add another blend function case for disabling plane alpha. Signed-off-by: Damien Lespiau Signed-off-by: vandita kulkarni --- drivers/gpu/drm/i915/i915_reg.h | 4 +++ drivers/gpu/drm/i915/intel_display.c | 47 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_drv.h | 3 +++ drivers/gpu/drm/i915/intel_sprite.c | 9 +++++-- 4 files changed, 61 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9464ba3..4d0c39d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5515,6 +5515,10 @@ enum skl_disp_power_wells { #define PLANE_KEYMAX(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) +#define PLANE_KEYMAX_ALPHA_MASK 0x00ffffff +#define PLANE_KEY_MASK_ALPHA_EN 31 +#define PLANE_KEY_MAX_ALPHA_SHIFT 24 + #define _PLANE_BUF_CFG_1_B 0x7127c #define _PLANE_BUF_CFG_2_B 0x7137c #define _PLANE_BUF_CFG_1(pipe) \ diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 037407f..31755f2 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3032,6 +3032,8 @@ static void skylake_update_primary_plane(struct drm_plane *plane, struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_framebuffer *fb = plane_state->base.fb; struct drm_i915_gem_object *obj = intel_fb_obj(fb); + const struct drm_intel_sprite_colorkey *key = + &to_intel_plane_state(plane->state)->ckey; int pipe = intel_crtc->pipe; u32 plane_ctl, stride_div, stride; u32 tile_height, plane_offset, plane_size; @@ -3064,6 +3066,15 @@ static void skylake_update_primary_plane(struct drm_plane *plane, WARN_ON(drm_rect_width(&plane_state->src) == 0); + I915_WRITE(PLANE_KEYMAX(pipe, 0), (DRM_MODE_COLOR_ALPHA_8 + (plane_state->base.blend_mode.color) + << PLANE_KEY_MAX_ALPHA_SHIFT) | + (key->max_value & PLANE_KEYMAX_ALPHA_MASK)); + I915_WRITE(PLANE_KEYMSK(pipe, 0), + (plane_state->use_plane_alpha + << PLANE_KEY_MASK_ALPHA_EN) | + (key->channel_mask & GENMASK(0, 26))); + if (intel_rotation_90_or_270(rotation)) { int cpp = drm_format_plane_cpp(fb->pixel_format, 0); @@ -3146,6 +3157,7 @@ static int intel_plane_state_check_blend(struct drm_plane_state *plane_state) case DRM_BLEND_FUNC(AUTO, AUTO): if (has_per_pixel_blending) state->per_pixel_alpha = PRE_MULTIPLIED_ALPHA; + state->use_plane_alpha = false; break; /* fbs without an alpha channel, or dropping the alpha channel */ case DRM_BLEND_FUNC(ONE, ZERO): @@ -3158,6 +3170,7 @@ static int intel_plane_state_check_blend(struct drm_plane_state *plane_state) state->per_pixel_alpha = DROP_ALPHA; else state->per_pixel_alpha = PRE_MULTIPLIED_ALPHA; + state->use_plane_alpha = false; break; /* non pre-multiplied alpha */ case DRM_BLEND_FUNC(SRC_ALPHA, ONE_MINUS_SRC_ALPHA): @@ -3165,6 +3178,34 @@ static int intel_plane_state_check_blend(struct drm_plane_state *plane_state) state->per_pixel_alpha = DROP_ALPHA; else state->per_pixel_alpha = NON_PRE_MULTIPLIED_ALPHA; + state->use_plane_alpha = false; + break; + /* plane alpha */ + case DRM_BLEND_FUNC(CONSTANT_ALPHA, ONE_MINUS_CONSTANT_ALPHA): + state->use_plane_alpha = true; + break; + /* plane alpha, pre-multiplied fb */ + case DRM_BLEND_FUNC(CONSTANT_ALPHA, + ONE_MINUS_CONSTANT_ALPHA_TIMES_SRC_ALPHA): + if (!has_per_pixel_blending) + state->per_pixel_alpha = DROP_ALPHA; + else + state->per_pixel_alpha = PRE_MULTIPLIED_ALPHA; + /*TBD bspec check*/ + state->use_plane_alpha = true; + break; + /* plane alpha, non pre-multiplied fb */ + case DRM_BLEND_FUNC(CONSTANT_ALPHA_TIMES_SRC_ALPHA, + ONE_MINUS_CONSTANT_ALPHA_TIMES_SRC_ALPHA): + if (!has_per_pixel_blending) + state->per_pixel_alpha = DROP_ALPHA; + else + state->per_pixel_alpha = NON_PRE_MULTIPLIED_ALPHA; + state->use_plane_alpha = true; + break; + /* drop plane alpha */ + case DRM_BLEND_FUNC(ZERO, ONE): + state->use_plane_alpha = false; break; default: return -EINVAL; @@ -14228,6 +14269,12 @@ void intel_plane_add_blend_properties(struct intel_plane *plane) if (prop) drm_object_attach_property(&plane->base.base, prop, DRM_BLEND_FUNC(AUTO, AUTO)); + + prop = dev->mode_config.prop_blend_color; + if (prop) + drm_object_attach_property(&plane->base.base, prop, + DRM_MODE_COLOR(0xffff, 0xffff, + 0xffff, 0xffff)); } static int diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 1939440..d3cb36f 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -341,6 +341,9 @@ struct intel_plane_state { /* per pixel alpha channel state */ enum per_pixel_alpha_state per_pixel_alpha; + /* use per-plane alpha */ + bool use_plane_alpha; + /* async flip related structures */ struct drm_i915_gem_request *wait_req; }; diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 9474b76..851c09a 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -226,10 +226,15 @@ skl_update_plane(struct drm_plane *drm_plane, crtc_w--; crtc_h--; + I915_WRITE(PLANE_KEYMAX(pipe, plane), + (DRM_MODE_COLOR_ALPHA_8(plane_state->base.blend_mode.color) + << 24) | (key->max_value & 0x00ffffff)); + I915_WRITE(PLANE_KEYMSK(pipe, plane), + (plane_state->use_plane_alpha << 31) | + (key->channel_mask & GENMASK(0, 26))); + if (key->flags) { I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value); - I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value); - I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask); } if (key->flags & I915_SET_COLORKEY_DESTINATION)