@@ -743,7 +743,7 @@ struct amdgpu_ib {
struct amdgpu_user_fence *user;
unsigned vm_id;
uint64_t vm_pd_addr;
- struct amdgpu_ctx *ctx;
+ uint64_t ctx;
uint32_t gds_base, gds_size;
uint32_t gws_base, gws_size;
uint32_t oa_base, oa_size;
@@ -806,7 +806,7 @@ struct amdgpu_ring {
unsigned wptr_offs;
unsigned next_rptr_offs;
unsigned fence_offs;
- struct amdgpu_ctx *current_ctx;
+ uint64_t current_ctx;
enum amdgpu_ring_type type;
char name[16];
unsigned cond_exe_offs;
@@ -741,7 +741,7 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
ib->length_dw = chunk_ib->ib_bytes / 4;
ib->flags = chunk_ib->flags;
- ib->ctx = parser->ctx;
+ ib->ctx = parser->ctx->rings[ring->idx].entity.fence_context;
j++;
}
@@ -121,7 +121,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
{
struct amdgpu_device *adev = ring->adev;
struct amdgpu_ib *ib = &ibs[0];
- struct amdgpu_ctx *ctx, *old_ctx;
+ uint64_t ctx, old_ctx;
struct fence *hwf;
struct amdgpu_vm *vm = NULL;
unsigned i, patch_offset = ~0;