diff mbox

[v2,7/7] drm/i915: Check pixel rate for DP to VGA dongle

Message ID 1463404773-5167-8-git-send-email-mika.kahola@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Mika Kahola May 16, 2016, 1:19 p.m. UTC 
Prep work to improve DP branch device handling.

Filter out a mode that exceeds the max pixel rate setting
for DP to VGA dongle. This is defined in DPCD register 0x81
if detailed cap info i.e. info field is 4 bytes long and
it is available for DP downstream port.

The register defines the pixel rate divided by 8 in MP/s.

v2: DPCD read outs and computation moved to drm (Ville, Daniel)

Signed-off-by: Mika Kahola <mika.kahola@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 11 +++++++++++
 1 file changed, 11 insertions(+)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3633002..5ec6287 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -201,6 +201,12 @@  intel_dp_mode_valid(struct drm_connector *connector,
 	int max_rate, mode_rate, max_lanes, max_link_clock;
 	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
 
+	/* DP to VGA dongle may define max pixel rate in DPCD */
+	if (intel_dp->bd.present &&
+	    (intel_dp->bd.type & DP_DS_PORT_TYPE_VGA) &&
+	    (intel_dp->bd.dfp.vga.dot_clk > 0))
+		max_dotclk = min(max_dotclk, intel_dp->bd.dfp.vga.dot_clk);
+
 	if (is_edp(intel_dp) && fixed_mode) {
 		if (mode->hdisplay > fixed_mode->hdisplay)
 			return MODE_PANEL;
@@ -4575,6 +4581,7 @@  intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	enum intel_display_power_domain power_domain;
 	enum irqreturn ret = IRQ_NONE;
+	int err;
 
 	if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
 	    intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
@@ -4599,6 +4606,10 @@  intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
 	power_domain = intel_display_port_aux_power_domain(intel_encoder);
 	intel_display_power_get(dev_priv, power_domain);
 
+	err = drm_dp_bd(&intel_dp->aux, &intel_dp->bd);
+	if (err < 0)
+		DRM_DEBUG_KMS("error reading DPCD[0x80] for DP branch device\n");
+
 	if (long_hpd) {
 		/* indicate that we need to restart link training */
 		intel_dp->train_set_valid = false;