From patchwork Mon May 16 13:19:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kahola X-Patchwork-Id: 9110381 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id F1DCCBF440 for ; Tue, 17 May 2016 08:09:05 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 225BC20303 for ; Tue, 17 May 2016 08:09:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 307C72034A for ; Tue, 17 May 2016 08:09:04 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A84D96E652; Tue, 17 May 2016 08:08:48 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id 8072E6E437; Mon, 16 May 2016 13:19:54 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP; 16 May 2016 06:19:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.24,627,1455004800"; d="scan'208";a="982011325" Received: from sorvi.fi.intel.com ([10.237.72.50]) by fmsmga002.fm.intel.com with ESMTP; 16 May 2016 06:19:52 -0700 From: Mika Kahola To: dri-devel@lists.freedesktop.org Subject: [PATCH v2 7/7] drm/i915: Check pixel rate for DP to VGA dongle Date: Mon, 16 May 2016 16:19:33 +0300 Message-Id: <1463404773-5167-8-git-send-email-mika.kahola@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1463404773-5167-1-git-send-email-mika.kahola@intel.com> References: <1463404773-5167-1-git-send-email-mika.kahola@intel.com> X-Mailman-Approved-At: Tue, 17 May 2016 08:08:36 +0000 Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org, jim.bish@intel.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Prep work to improve DP branch device handling. Filter out a mode that exceeds the max pixel rate setting for DP to VGA dongle. This is defined in DPCD register 0x81 if detailed cap info i.e. info field is 4 bytes long and it is available for DP downstream port. The register defines the pixel rate divided by 8 in MP/s. v2: DPCD read outs and computation moved to drm (Ville, Daniel) Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/intel_dp.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 3633002..5ec6287 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -201,6 +201,12 @@ intel_dp_mode_valid(struct drm_connector *connector, int max_rate, mode_rate, max_lanes, max_link_clock; int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + /* DP to VGA dongle may define max pixel rate in DPCD */ + if (intel_dp->bd.present && + (intel_dp->bd.type & DP_DS_PORT_TYPE_VGA) && + (intel_dp->bd.dfp.vga.dot_clk > 0)) + max_dotclk = min(max_dotclk, intel_dp->bd.dfp.vga.dot_clk); + if (is_edp(intel_dp) && fixed_mode) { if (mode->hdisplay > fixed_mode->hdisplay) return MODE_PANEL; @@ -4575,6 +4581,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) struct drm_i915_private *dev_priv = dev->dev_private; enum intel_display_power_domain power_domain; enum irqreturn ret = IRQ_NONE; + int err; if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && intel_dig_port->base.type != INTEL_OUTPUT_HDMI) @@ -4599,6 +4606,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) power_domain = intel_display_port_aux_power_domain(intel_encoder); intel_display_power_get(dev_priv, power_domain); + err = drm_dp_bd(&intel_dp->aux, &intel_dp->bd); + if (err < 0) + DRM_DEBUG_KMS("error reading DPCD[0x80] for DP branch device\n"); + if (long_hpd) { /* indicate that we need to restart link training */ intel_dp->train_set_valid = false;