From patchwork Fri May 20 21:50:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 9130089 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A0D306048B for ; Fri, 20 May 2016 21:50:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 97DDE27BF4 for ; Fri, 20 May 2016 21:50:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8CD6427CF9; Fri, 20 May 2016 21:50:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_WEB, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 47D9927BF4 for ; Fri, 20 May 2016 21:50:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 302BE6E125; Fri, 20 May 2016 21:50:55 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-io0-x244.google.com (mail-io0-x244.google.com [IPv6:2607:f8b0:4001:c06::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id 303596E125 for ; Fri, 20 May 2016 21:50:49 +0000 (UTC) Received: by mail-io0-x244.google.com with SMTP id a79so12152681ioe.3 for ; Fri, 20 May 2016 14:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uxIQf+ySi/3+Jt5qmGBHH05shL0MqQer9YDZQcKV+Dw=; b=hhjMRtUEGKNdwjajZB+jRrGv7aKNhws64dZUTIXadx51ghBkVpScgW8X5Z6A8rgfQ4 KnQMaubQAw6y+nTpRu7dWQ93N+JxFyI+lgrkbfBqPt6nr5tGHPsOZNHkEDs5MAaVNVO1 WtKbo1FMUWJWM0VbLUWDsglRLhT/fXr9o0yrPGN1iMmZ4+Xx0yzvzPXxVhenjW0UWLQF DA3foVQkOyDpWl5z4AKugj1thvj7hyFtu7AF6i+6W9BuxREmEvNkiGX7UwznHcxCRJ5L maxgeD23qoIKzIqjaS1FphtVsrUfdWTu1qN1aChYKLVVZkGqyS8cJffseHlDddbSvHyW TuAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uxIQf+ySi/3+Jt5qmGBHH05shL0MqQer9YDZQcKV+Dw=; b=hUFwj3ojEr9m9o64DVCYefVMPfET7DHtpTp6KYVRnOO/gBj86u4DoCAO3uZwbroq6s rSg4fXGXilx1v1Tl1zfFnhSvhpbvmGJNBPt8c4KEspAh9bwi6eiPnxW5MX06QktWGVyT Sw85A2HGjKhUmqMITC8FnOtTcyWROgMew3mWNW3Fb4zPg+G60kSOe5yk+Qxnu9gL92Av pVpKx0vRnlehvf//wz47dojP3/TAmYCvGoNxfOx+vnilSjHGJ+Er/fnQkc9K8K5gliNM wX8U50nDukUUjb/nr2pgM13KwmKy3EwvHuOCL586NFqi/z8hOsSAVFquj33t1exCyhOY c6jw== X-Gm-Message-State: AOPr4FXkIAHvVpt0Pe0ApOcYhI4zNAzEJhreWUn26wgvFpEC/pkMzhA34clibN52cPZQew== X-Received: by 10.107.33.146 with SMTP id h140mr4829061ioh.30.1463781048303; Fri, 20 May 2016 14:50:48 -0700 (PDT) Received: from cm.amd.com ([165.204.55.251]) by smtp.gmail.com with ESMTPSA id vh5sm35832igb.21.2016.05.20.14.50.47 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 20 May 2016 14:50:47 -0700 (PDT) From: Alex Deucher X-Google-Original-From: Alex Deucher To: dri-devel@lists.freedesktop.org Subject: [PATCH 4/6] drm/amdgpu/si: use dma instance offset array directly Date: Fri, 20 May 2016 17:50:37 -0400 Message-Id: <1463781039-722-4-git-send-email-alexander.deucher@amd.com> X-Mailer: git-send-email 2.5.5 In-Reply-To: <1463781039-722-1-git-send-email-alexander.deucher@amd.com> References: <1463781039-722-1-git-send-email-alexander.deucher@amd.com> Cc: Alex Deucher X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP No need for a local variable. Also, fix a few registers that did not have the per instance offset properly added. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/si_dma.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 7e65b64..4dad157 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -154,16 +154,15 @@ static void si_dma_stop(struct amdgpu_device *adev) static int si_dma_start(struct amdgpu_device *adev) { struct amdgpu_ring *ring; - u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz, reg_offset; + u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; int i, r; uint64_t rptr_addr; for (i = 0; i < adev->sdma.num_instances; i++) { ring = &adev->sdma.instance[i].ring; - reg_offset = sdma_offsets[i]; - WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); - WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); + WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); + WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); /* Set ring buffer size in dwords */ rb_bufsz = order_base_2(ring->ring_size / 4); @@ -171,36 +170,36 @@ static int si_dma_start(struct amdgpu_device *adev) #ifdef __BIG_ENDIAN rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; #endif - WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); + WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); /* Initialize the ring buffer's read and write pointers */ - WREG32(DMA_RB_RPTR + reg_offset, 0); - WREG32(DMA_RB_WPTR + reg_offset, 0); + WREG32(DMA_RB_RPTR + sdma_offsets[i], 0); + WREG32(DMA_RB_WPTR + sdma_offsets[i], 0); rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); - WREG32(DMA_RB_RPTR_ADDR_LO, lower_32_bits(rptr_addr)); - WREG32(DMA_RB_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); + WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); + WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF); rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; - WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8); + WREG32(DMA_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); /* enable DMA IBs */ ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE; #ifdef __BIG_ENDIAN ib_cntl |= DMA_IB_SWAP_ENABLE; #endif - WREG32(DMA_IB_CNTL + reg_offset, ib_cntl); + WREG32(DMA_IB_CNTL + sdma_offsets[i], ib_cntl); - dma_cntl = RREG32(DMA_CNTL + reg_offset); + dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]); dma_cntl &= ~CTXEMPTY_INT_ENABLE; - WREG32(DMA_CNTL + reg_offset, dma_cntl); + WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl); ring->wptr = 0; - WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2); + WREG32(DMA_RB_WPTR + sdma_offsets[i], ring->wptr << 2); - WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE); + WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); ring->ready = true;