From patchwork Mon May 23 10:50:53 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kahola X-Patchwork-Id: 9131559 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9354360459 for ; Mon, 23 May 2016 11:02:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 87AFB2822E for ; Mon, 23 May 2016 11:02:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7CC3D28233; Mon, 23 May 2016 11:02:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4B3922822E for ; Mon, 23 May 2016 11:02:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9F9396E5A8; Mon, 23 May 2016 11:02:49 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id AA4716E582; Mon, 23 May 2016 10:51:18 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 23 May 2016 03:51:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,355,1459839600"; d="scan'208";a="982783342" Received: from sorvi.fi.intel.com ([10.237.72.50]) by orsmga002.jf.intel.com with ESMTP; 23 May 2016 03:51:15 -0700 From: Mika Kahola To: dri-devel@lists.freedesktop.org Subject: [PATCH v3 08/12] drm/i915: Check pixel rate for DP to VGA dongle Date: Mon, 23 May 2016 13:50:53 +0300 Message-Id: <1464000657-16867-9-git-send-email-mika.kahola@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1464000657-16867-1-git-send-email-mika.kahola@intel.com> References: <1464000657-16867-1-git-send-email-mika.kahola@intel.com> X-Mailman-Approved-At: Mon, 23 May 2016 11:02:04 +0000 Cc: intel-gfx@lists.freedesktop.org, jim.bride@intel.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Prep work to improve DP branch device handling. Filter out a mode that exceeds the max pixel rate setting for DP to VGA dongle. This is defined in DPCD register 0x81 if detailed cap info i.e. info field is 4 bytes long and it is available for DP downstream port. The register defines the pixel rate divided by 8 in MP/s. v2: DPCD read outs and computation moved to drm (Ville, Daniel) v3: Sink pixel rate computation moved to drm_dp_max_sink_dotclock() function (Daniel) Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/intel_dp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index cccf9bc..5e16063 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -201,6 +201,8 @@ intel_dp_mode_valid(struct drm_connector *connector, int max_rate, mode_rate, max_lanes, max_link_clock; int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + max_dotclk = drm_dp_max_sink_dotclock(max_dotclk, &intel_dp->bd); + if (is_edp(intel_dp) && fixed_mode) { if (mode->hdisplay > fixed_mode->hdisplay) return MODE_PANEL; @@ -4576,6 +4578,7 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) struct drm_i915_private *dev_priv = dev->dev_private; enum intel_display_power_domain power_domain; enum irqreturn ret = IRQ_NONE; + int err; if (intel_dig_port->base.type != INTEL_OUTPUT_EDP && intel_dig_port->base.type != INTEL_OUTPUT_HDMI) @@ -4600,6 +4603,10 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) power_domain = intel_display_port_aux_power_domain(intel_encoder); intel_display_power_get(dev_priv, power_domain); + err = drm_dp_bd(&intel_dp->aux, &intel_dp->bd); + if (err < 0) + DRM_DEBUG_KMS("error reading DPCD[0x80] for DP branch device\n"); + if (long_hpd) { /* indicate that we need to restart link training */ intel_dp->train_set_valid = false;