From patchwork Mon Jun 6 13:29:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kahola X-Patchwork-Id: 9159671 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3EF6960572 for ; Tue, 7 Jun 2016 00:41:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2F81328326 for ; Tue, 7 Jun 2016 00:41:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2343428350; Tue, 7 Jun 2016 00:41:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E6B0928326 for ; Tue, 7 Jun 2016 00:41:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A7E996E6A0; Tue, 7 Jun 2016 00:41:24 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 6F4176E51C; Mon, 6 Jun 2016 13:29:34 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP; 06 Jun 2016 06:29:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.26,427,1459839600"; d="scan'208";a="969814885" Received: from sorvi.fi.intel.com ([10.237.72.50]) by orsmga001.jf.intel.com with ESMTP; 06 Jun 2016 06:29:33 -0700 From: Mika Kahola To: dri-devel@lists.freedesktop.org Subject: [PATCH v4 09/11] drm/i915: Check pixel rate for DP to VGA dongle Date: Mon, 6 Jun 2016 16:29:11 +0300 Message-Id: <1465219753-3737-10-git-send-email-mika.kahola@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1465219753-3737-1-git-send-email-mika.kahola@intel.com> References: <1465219753-3737-1-git-send-email-mika.kahola@intel.com> X-Mailman-Approved-At: Tue, 07 Jun 2016 00:40:40 +0000 Cc: daniel.vetter@ffwll.ch, intel-gfx@lists.freedesktop.org, jim.bride@linux.intel.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Filter out a mode that exceeds the max pixel rate setting for DP to VGA dongle. This is defined in DPCD register 0x81 if detailed cap info i.e. info field is 4 bytes long and it is available for DP downstream port. The register defines the pixel rate divided by 8 in MP/s. v2: DPCD read outs and computation moved to drm (Ville, Daniel) v3: Sink pixel rate computation moved to drm_dp_max_sink_dotclock() function (Daniel) v4: Use of drm_dp_helper.c routines to compute max pixel clock (Ville) Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/intel_dp.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 096acbf0..1b94347 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -200,6 +200,23 @@ intel_dp_mode_valid(struct drm_connector *connector, int target_clock = mode->clock; int max_rate, mode_rate, max_lanes, max_link_clock; int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; + bool is_branch_device; + int max_dp_clk; + int type; + uint8_t port_cap[4]; + + is_branch_device = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & + DP_DWN_STRM_PORT_PRESENT; + + if (is_branch_device) { + drm_dp_downstream_port_cap(&intel_dp->aux, intel_dp->dpcd, port_cap); + type = drm_dp_downstream_type(intel_dp->dpcd, port_cap); + max_dp_clk = drm_dp_downstream_max_clock(intel_dp->dpcd, port_cap); + + if ((type == DP_DS_PORT_TYPE_VGA) && (max_dp_clk > 0)) { + max_dotclk = min(max_dotclk, max_dp_clk); + } + } if (is_edp(intel_dp) && fixed_mode) { if (mode->hdisplay > fixed_mode->hdisplay)