From patchwork Tue Jun 7 14:24:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 9161529 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3DC9F60467 for ; Tue, 7 Jun 2016 14:24:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2E56425404 for ; Tue, 7 Jun 2016 14:24:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 234392793B; Tue, 7 Jun 2016 14:24:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_WEB, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 885A725404 for ; Tue, 7 Jun 2016 14:24:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1052A6E79B; Tue, 7 Jun 2016 14:24:29 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-it0-x243.google.com (mail-it0-x243.google.com [IPv6:2607:f8b0:4001:c0b::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id 12D036E79B for ; Tue, 7 Jun 2016 14:24:27 +0000 (UTC) Received: by mail-it0-x243.google.com with SMTP id u203so12493446itc.0 for ; Tue, 07 Jun 2016 07:24:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=phcIF/iq1uOzoHfElSB6rZwFTVuMHnQJ3/CrFyEa9n8=; b=gZs8NG7RxM9V72mkBjAHyDQHMa4nxV1tBqa0KIdgJvzVAIyFHfuLnG6UjPQNijXJ7p wSTgYHHCPv/ZHTIohd+RIzd3qQjyCVmCJSqooJQdRycsANbQ8Eg7nC4tPQ/n1ABryFGz kVAlEwHDSHtUam3fbjDqTYIiUEszoi75q/oMQiDgeN8Zawtz2QuRue3VJUtvZxLxZThg qDqnpQbth5Uwojc376tGadAX4cyjlTz5VP+hVE/69MJ82j5JPgSE1Hfz0FbS9nq/l+TL yMQJz+iGtwEeWhXlHL4pKP4PEmkQi5UC2HrJ0D1r0RZiC4sQTEEwG4cJgweVfFlPJEG0 F/jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=phcIF/iq1uOzoHfElSB6rZwFTVuMHnQJ3/CrFyEa9n8=; b=JNwTf2NSuPN3bthKHxOfi21X19P0TBk6DMDjgRu4HSDyfJ9kxftizzXHMFUtEknmrh It89pOjIBHmVBR3pVbcbnRE4B4n/N4zZnOaypXMVlcpQtitBHaxSqS9rKjSapAzgM2RE 9uqj9d4dTNBNGE9g3jGc7OQ+mjeoOxipRwuzP9ATlboJpO3tR7yIL1EO2IhMNM5TJx20 walU9ucUHKP/+SvLPCrS3EAX5kf1YKWsZQ609+tWkaU/X/cj8u+ePfZN3Xef2P4RJSnL vbXiK0wipz3Mi7fh3agD2ZWY13sjL2kv7eX0+vtqC/FybPpoRfxD3y/MEzFF4SRatiw0 LgUA== X-Gm-Message-State: ALyK8tIGk1WkU4nWMzBJSTCLih8diZnTxoTPePfjD+JPSoIrGguCOFewHBW3R565lLSPsQ== X-Received: by 10.107.59.147 with SMTP id i141mr30740953ioa.90.1465309466041; Tue, 07 Jun 2016 07:24:26 -0700 (PDT) Received: from cm.amd.com ([165.204.55.251]) by smtp.gmail.com with ESMTPSA id j9sm4899056itj.8.2016.06.07.07.24.25 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 07 Jun 2016 07:24:25 -0700 (PDT) From: Alex Deucher X-Google-Original-From: Alex Deucher To: dri-devel@lists.freedesktop.org Subject: [PATCH 1/2] drm/amdgpu: add return value for pci config reset Date: Tue, 7 Jun 2016 10:24:17 -0400 Message-Id: <1465309458-25050-1-git-send-email-alexander.deucher@amd.com> X-Mailer: git-send-email 2.5.5 MIME-Version: 1.0 Cc: Alex Deucher X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Chunming Zhou So we know whether or not the reset succeeded. Signed-off-by: Chunming Zhou Reviewed-by: Christian König Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cik.c | 14 ++++++++++---- drivers/gpu/drm/amd/amdgpu/vi.c | 12 +++++++----- 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 07bc795..924c85c 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1152,10 +1152,11 @@ static void kv_restore_regs_for_reset(struct amdgpu_device *adev, WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute); } -static void cik_gpu_pci_config_reset(struct amdgpu_device *adev) +static int cik_gpu_pci_config_reset(struct amdgpu_device *adev) { struct kv_reset_save_regs kv_save = { 0 }; u32 i; + int r = -EINVAL; dev_info(adev->dev, "GPU pci config reset\n"); @@ -1171,14 +1172,18 @@ static void cik_gpu_pci_config_reset(struct amdgpu_device *adev) /* wait for asic to come out of reset */ for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) + if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) { + r = 0; break; + } udelay(1); } /* does asic init need to be run first??? */ if (adev->flags & AMD_IS_APU) kv_restore_regs_for_reset(adev, &kv_save); + + return r; } static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung) @@ -1204,13 +1209,14 @@ static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hu */ static int cik_asic_reset(struct amdgpu_device *adev) { + int r; cik_set_bios_scratch_engine_hung(adev, true); - cik_gpu_pci_config_reset(adev); + r = cik_gpu_pci_config_reset(adev); cik_set_bios_scratch_engine_hung(adev, false); - return 0; + return r; } static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock, diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 38bcc05..dcc937e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -583,7 +583,7 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, return -EINVAL; } -static void vi_gpu_pci_config_reset(struct amdgpu_device *adev) +static int vi_gpu_pci_config_reset(struct amdgpu_device *adev) { u32 i; @@ -599,10 +599,10 @@ static void vi_gpu_pci_config_reset(struct amdgpu_device *adev) /* wait for asic to come out of reset */ for (i = 0; i < adev->usec_timeout; i++) { if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) - break; + return 0; udelay(1); } - + return -EINVAL; } static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung) @@ -628,13 +628,15 @@ static void vi_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hun */ static int vi_asic_reset(struct amdgpu_device *adev) { + int r; + vi_set_bios_scratch_engine_hung(adev, true); - vi_gpu_pci_config_reset(adev); + r = vi_gpu_pci_config_reset(adev); vi_set_bios_scratch_engine_hung(adev, false); - return 0; + return r; } static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,