From patchwork Wed Jun 29 09:17:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 9204583 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DDFD360757 for ; Wed, 29 Jun 2016 09:19:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CE2562862A for ; Wed, 29 Jun 2016 09:19:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C2B7228639; Wed, 29 Jun 2016 09:19:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 743672862A for ; Wed, 29 Jun 2016 09:19:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 067046E6A3; Wed, 29 Jun 2016 09:19:51 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from hqemgate15.nvidia.com (hqemgate15.nvidia.com [216.228.121.64]) by gabe.freedesktop.org (Postfix) with ESMTPS id D26A989A72 for ; Wed, 29 Jun 2016 09:18:37 +0000 (UTC) Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 29 Jun 2016 02:18:02 -0700 Received: from HQMAIL105.nvidia.com ([172.20.187.12]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 29 Jun 2016 02:17:22 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 29 Jun 2016 02:17:22 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 29 Jun 2016 09:18:35 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 29 Jun 2016 09:18:35 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Wed, 29 Jun 2016 09:18:35 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.21.132.149]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Wed, 29 Jun 2016 02:18:34 -0700 From: Jon Hunter To: Thierry Reding , David Airlie , Stephen Warren , Alexandre Courbot , Wolfram Sang , Rob Herring , Mark Rutland Subject: [PATCH V2 11/11] arm64: tegra: Add DPAUX pinctrl bindings Date: Wed, 29 Jun 2016 10:17:57 +0100 Message-ID: <1467191877-26017-12-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1467191877-26017-1-git-send-email-jonathanh@nvidia.com> References: <1467191877-26017-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, Jon Hunter , linux-gpio@vger.kernel.org, linux-i2c@vger.kernel.org, linux-tegra@vger.kernel.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add the DPAUX pinctrl states for the DPAUX nodes defining all three possible states of "aux", "i2c" and "off". Also add the 'i2c-bus' node for the DPAUX nodes so that the I2C driver core does not attempt to parse the pinctrl state nodes. Populate the nodes for the pinctrl clients of the DPAUX pin controller. There are two clients for each DPAUX instance, namely the SOR and one of the I2C adapters. The SOR clients may used the DPAUX pins in either AUX or I2C modes and so for these devices we don't define any of the generic pinctrl states (default, idle, etc) because the SOR driver will directly set the state needed. For I2C clients only the I2C mode is used and so we can simplify matters by using the generic pinctrl states for default and idle. Signed-off-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 54 ++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index ef317f0d773f..65b829b762bb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -36,6 +36,26 @@ reset-names = "dpaux"; power-domains = <&pd_sor>; status = "disabled"; + + state_dpaux1_aux: pinmux-aux { + groups = "dpaux-io"; + function = "aux"; + }; + + state_dpaux1_i2c: pinmux-i2c { + groups = "dpaux-io"; + function = "i2c"; + }; + + state_dpaux1_off: pinmux-off { + groups = "dpaux-io"; + function = "off"; + }; + + i2c-bus { + #address-cells = <1>; + #size-cells = <0>; + }; }; vi@54080000 { @@ -155,6 +175,10 @@ clock-names = "sor", "parent", "dp", "safe"; resets = <&tegra_car 182>; reset-names = "sor"; + pinctrl-0 = <&state_dpaux_aux>; + pinctrl-1 = <&state_dpaux_i2c>; + pinctrl-2 = <&state_dpaux_off>; + pinctrl-names = "aux", "i2c", "off"; power-domains = <&pd_sor>; status = "disabled"; }; @@ -170,6 +194,10 @@ clock-names = "sor", "parent", "dp", "safe"; resets = <&tegra_car 183>; reset-names = "sor"; + pinctrl-0 = <&state_dpaux1_aux>; + pinctrl-1 = <&state_dpaux1_i2c>; + pinctrl-2 = <&state_dpaux1_off>; + pinctrl-names = "aux", "i2c", "off"; power-domains = <&pd_sor>; status = "disabled"; }; @@ -185,6 +213,26 @@ reset-names = "dpaux"; power-domains = <&pd_sor>; status = "disabled"; + + state_dpaux_aux: pinmux-aux { + groups = "dpaux-io"; + function = "aux"; + }; + + state_dpaux_i2c: pinmux-i2c { + groups = "dpaux-io"; + function = "i2c"; + }; + + state_dpaux_off: pinmux-off { + groups = "dpaux-io"; + function = "off"; + }; + + i2c-bus { + #address-cells = <1>; + #size-cells = <0>; + }; }; isp@54600000 { @@ -482,6 +530,9 @@ reset-names = "i2c"; dmas = <&apbdma 26>, <&apbdma 26>; dma-names = "rx", "tx"; + pinctrl-0 = <&state_dpaux1_i2c>; + pinctrl-1 = <&state_dpaux1_off>; + pinctrl-names = "default", "idle"; status = "disabled"; }; @@ -512,6 +563,9 @@ reset-names = "i2c"; dmas = <&apbdma 30>, <&apbdma 30>; dma-names = "rx", "tx"; + pinctrl-0 = <&state_dpaux_i2c>; + pinctrl-1 = <&state_dpaux_off>; + pinctrl-names = "default", "idle"; status = "disabled"; };