From patchwork Fri Jul 1 13:21:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 9209891 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2CB73607D8 for ; Fri, 1 Jul 2016 13:21:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1DED728325 for ; Fri, 1 Jul 2016 13:21:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 12AE2286B0; Fri, 1 Jul 2016 13:21:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D275B28325 for ; Fri, 1 Jul 2016 13:21:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DE4E36EA7B; Fri, 1 Jul 2016 13:21:49 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from hqemgate16.nvidia.com (hqemgate16.nvidia.com [216.228.121.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 79D196EA7B for ; Fri, 1 Jul 2016 13:21:48 +0000 (UTC) Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Fri, 01 Jul 2016 06:21:10 -0700 Received: from HQMAIL106.nvidia.com ([172.18.146.12]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 01 Jul 2016 06:20:26 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 01 Jul 2016 06:20:26 -0700 Received: from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 1 Jul 2016 13:21:47 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL112.nvidia.com (172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 1 Jul 2016 13:21:47 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Fri, 1 Jul 2016 13:21:46 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.21.132.149]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Fri, 01 Jul 2016 06:21:46 -0700 From: Jon Hunter To: Thierry Reding , David Airlie , Stephen Warren , Alexandre Courbot Subject: [PATCH 3/3] arm64: tegra: Populate SOR power domain for DSI Date: Fri, 1 Jul 2016 14:21:39 +0100 Message-ID: <1467379299-11961-3-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1467379299-11961-1-git-send-email-jonathanh@nvidia.com> References: <1467379299-11961-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Jon Hunter X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The DSI device requires that the SOR power partition is enabled when active. Populate this power partition for the Tegra210 DSI nodes. Signed-off-by: Jon Hunter --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 99c5e9f69f72..2885a119b430 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -109,6 +109,7 @@ clock-names = "dsi", "lp", "parent"; resets = <&tegra_car 48>; reset-names = "dsi"; + power-domains = <&pd_sor>; nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ status = "disabled"; @@ -138,6 +139,7 @@ clock-names = "dsi", "lp", "parent"; resets = <&tegra_car 82>; reset-names = "dsi"; + power-domains = <&pd_sor>; nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ status = "disabled";