From patchwork Wed Jul 20 13:18:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 9239589 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 425E260574 for ; Wed, 20 Jul 2016 13:18:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 33A9726C2F for ; Wed, 20 Jul 2016 13:18:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2845E2787C; Wed, 20 Jul 2016 13:18:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C541126C2F for ; Wed, 20 Jul 2016 13:18:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 30CCA6E824; Wed, 20 Jul 2016 13:18:55 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id EC0166E82E; Wed, 20 Jul 2016 13:18:36 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP; 20 Jul 2016 06:18:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.28,394,1464678000"; d="scan'208"; a="1025552902" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga002.fm.intel.com with SMTP; 20 Jul 2016 06:18:33 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 20 Jul 2016 16:18:33 +0300 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Subject: [PATCH 6/7] drm/i915: Clean up rotation DSPCNTR/DVSCNTR/etc. setup Date: Wed, 20 Jul 2016 16:18:11 +0300 Message-Id: <1469020693-24356-7-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1469020693-24356-1-git-send-email-ville.syrjala@linux.intel.com> References: <1469020693-24356-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Cc: dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä Move the plane control register rotation setup away from the coordinate munging code. This will result in neater looking code once we add reflection support for CHV. Signed-off-by: Ville Syrjälä Reviewed-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_display.c | 28 ++++++++++++++-------------- drivers/gpu/drm/i915/intel_sprite.c | 28 +++++++++++++++------------- 2 files changed, 29 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 79c1a8b89d1d..88a7c4173715 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2674,6 +2674,9 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, obj->tiling_mode != I915_TILING_NONE) dspcntr |= DISPPLANE_TILED; + if (rotation & BIT(DRM_ROTATE_180)) + dspcntr |= DISPPLANE_ROTATE_180; + if (IS_G4X(dev)) dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; @@ -2689,8 +2692,6 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, } if (rotation & BIT(DRM_ROTATE_180)) { - dspcntr |= DISPPLANE_ROTATE_180; - x += (crtc_state->pipe_src_w - 1); y += (crtc_state->pipe_src_h - 1); @@ -2783,6 +2784,9 @@ static void ironlake_update_primary_plane(struct drm_plane *primary, if (obj->tiling_mode != I915_TILING_NONE) dspcntr |= DISPPLANE_TILED; + if (rotation & BIT(DRM_ROTATE_180)) + dspcntr |= DISPPLANE_ROTATE_180; + if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; @@ -2792,19 +2796,15 @@ static void ironlake_update_primary_plane(struct drm_plane *primary, fb->pitches[0], rotation); linear_offset -= intel_crtc->dspaddr_offset; - if (rotation & BIT(DRM_ROTATE_180)) { - dspcntr |= DISPPLANE_ROTATE_180; - - if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { - x += (crtc_state->pipe_src_w - 1); - y += (crtc_state->pipe_src_h - 1); + /* HSW and BDW does this automagically in hardware */ + if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && + rotation & BIT(DRM_ROTATE_180)) { + x += (crtc_state->pipe_src_w - 1); + y += (crtc_state->pipe_src_h - 1); - /* Finding the last pixel of the last line of the display - data and adding to linear_offset*/ - linear_offset += - (crtc_state->pipe_src_h - 1) * fb->pitches[0] + - (crtc_state->pipe_src_w - 1) * cpp; - } + linear_offset += + (crtc_state->pipe_src_h - 1) * fb->pitches[0] + + (crtc_state->pipe_src_w - 1) * cpp; } intel_crtc->adjusted_x = x; diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 6b815d57d75a..14173f53f520 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -433,6 +433,9 @@ vlv_update_plane(struct drm_plane *dplane, if (obj->tiling_mode != I915_TILING_NONE) sprctl |= SP_TILED; + if (rotation & BIT(DRM_ROTATE_180)) + sprctl |= SP_ROTATE_180; + /* Sizes are 0 based */ src_w--; src_h--; @@ -445,8 +448,6 @@ vlv_update_plane(struct drm_plane *dplane, linear_offset -= sprsurf_offset; if (rotation & BIT(DRM_ROTATE_180)) { - sprctl |= SP_ROTATE_180; - x += src_w; y += src_h; linear_offset += src_h * fb->pitches[0] + src_w * cpp; @@ -555,6 +556,9 @@ ivb_update_plane(struct drm_plane *plane, if (obj->tiling_mode != I915_TILING_NONE) sprctl |= SPRITE_TILED; + if (rotation & BIT(DRM_ROTATE_180)) + sprctl |= SPRITE_ROTATE_180; + if (IS_HASWELL(dev) || IS_BROADWELL(dev)) sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE; else @@ -577,15 +581,12 @@ ivb_update_plane(struct drm_plane *plane, fb->pitches[0], rotation); linear_offset -= sprsurf_offset; - if (rotation & BIT(DRM_ROTATE_180)) { - sprctl |= SPRITE_ROTATE_180; - - /* HSW and BDW does this automagically in hardware */ - if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { - x += src_w; - y += src_h; - linear_offset += src_h * fb->pitches[0] + src_w * cpp; - } + /* HSW and BDW does this automagically in hardware */ + if (!IS_HASWELL(dev) && !IS_BROADWELL(dev) && + rotation & BIT(DRM_ROTATE_180)) { + x += src_w; + y += src_h; + linear_offset += src_h * fb->pitches[0] + src_w * cpp; } if (key->flags) { @@ -696,6 +697,9 @@ ilk_update_plane(struct drm_plane *plane, if (obj->tiling_mode != I915_TILING_NONE) dvscntr |= DVS_TILED; + if (rotation & BIT(DRM_ROTATE_180)) + dvscntr |= DVS_ROTATE_180; + if (IS_GEN6(dev)) dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */ @@ -715,8 +719,6 @@ ilk_update_plane(struct drm_plane *plane, linear_offset -= dvssurf_offset; if (rotation & BIT(DRM_ROTATE_180)) { - dvscntr |= DVS_ROTATE_180; - x += src_w; y += src_h; linear_offset += src_h * fb->pitches[0] + src_w * cpp;