From patchwork Wed Jul 20 13:18:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 9239591 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BFEF960574 for ; Wed, 20 Jul 2016 13:19:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B12DE26C9B for ; Wed, 20 Jul 2016 13:19:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A4F4F26C2F; Wed, 20 Jul 2016 13:19:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5128426C2F for ; Wed, 20 Jul 2016 13:19:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AB1426E82B; Wed, 20 Jul 2016 13:19:02 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTP id CA1D36E82C; Wed, 20 Jul 2016 13:18:40 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 20 Jul 2016 06:18:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,394,1464678000"; d="scan'208";a="999033595" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga001.jf.intel.com with SMTP; 20 Jul 2016 06:18:37 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 20 Jul 2016 16:18:36 +0300 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Subject: [PATCH 7/7] drm/i915: Add horizontal mirroring support for CHV pipe B planes Date: Wed, 20 Jul 2016 16:18:12 +0300 Message-Id: <1469020693-24356-8-git-send-email-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1469020693-24356-1-git-send-email-ville.syrjala@linux.intel.com> References: <1469020693-24356-1-git-send-email-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Cc: dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä The primary and sprite planes on CHV pipe B support horizontal mirroring. Expose it to the world. Sadly the hardware ignores the mirror bit when the rotate bit is set, so we'll have to reject the 180+X case. Signed-off-by: Ville Syrjälä Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/intel_atomic_plane.c | 8 ++++++++ drivers/gpu/drm/i915/intel_display.c | 10 ++++++++++ drivers/gpu/drm/i915/intel_sprite.c | 10 ++++++++++ 3 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c index c19eb9a0cd4a..0a019eacfede 100644 --- a/drivers/gpu/drm/i915/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c @@ -180,6 +180,14 @@ static int intel_plane_atomic_check(struct drm_plane *plane, } } + /* CHV ignores the mirror bit when the rotate bit is set :( */ + if (IS_CHERRYVIEW(plane->dev) && + state->rotation & BIT(DRM_ROTATE_180) && + state->rotation & BIT(DRM_REFLECT_X)) { + DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n"); + return -EINVAL; + } + intel_state->visible = false; ret = intel_plane->check_plane(plane, crtc_state, intel_state); if (ret) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 88a7c4173715..edb1809a642d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2677,6 +2677,9 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, if (rotation & BIT(DRM_ROTATE_180)) dspcntr |= DISPPLANE_ROTATE_180; + if (rotation & BIT(DRM_REFLECT_X)) + dspcntr |= DISPPLANE_MIRROR; + if (IS_G4X(dev)) dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; @@ -2700,6 +2703,9 @@ static void i9xx_update_primary_plane(struct drm_plane *primary, linear_offset += (crtc_state->pipe_src_h - 1) * fb->pitches[0] + (crtc_state->pipe_src_w - 1) * cpp; + } else if (rotation & BIT(DRM_REFLECT_X)) { + x += (crtc_state->pipe_src_w - 1); + linear_offset += (crtc_state->pipe_src_w - 1) * cpp; } intel_crtc->adjusted_x = x; @@ -14295,6 +14301,10 @@ static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, supported_rotations = BIT(DRM_ROTATE_0) | BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_180) | BIT(DRM_ROTATE_270); + } else if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { + supported_rotations = + BIT(DRM_ROTATE_0) | BIT(DRM_ROTATE_180) | + BIT(DRM_REFLECT_X); } else if (INTEL_INFO(dev)->gen >= 4) { supported_rotations = BIT(DRM_ROTATE_0) | BIT(DRM_ROTATE_180); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 14173f53f520..4d6cd1a02e34 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -436,6 +436,9 @@ vlv_update_plane(struct drm_plane *dplane, if (rotation & BIT(DRM_ROTATE_180)) sprctl |= SP_ROTATE_180; + if (rotation & BIT(DRM_REFLECT_X)) + sprctl |= SP_MIRROR; + /* Sizes are 0 based */ src_w--; src_h--; @@ -451,6 +454,9 @@ vlv_update_plane(struct drm_plane *dplane, x += src_w; y += src_h; linear_offset += src_h * fb->pitches[0] + src_w * cpp; + } else if (rotation & BIT(DRM_REFLECT_X)) { + x += src_w; + linear_offset += src_w * cpp; } if (key->flags) { @@ -1128,6 +1134,10 @@ intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane) supported_rotations = BIT(DRM_ROTATE_0) | BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_180) | BIT(DRM_ROTATE_270); + } else if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { + supported_rotations = + BIT(DRM_ROTATE_0) | BIT(DRM_ROTATE_180) | + BIT(DRM_REFLECT_X); } else { supported_rotations = BIT(DRM_ROTATE_0) | BIT(DRM_ROTATE_180);