From patchwork Thu Jul 21 19:23:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: cpaul@redhat.com X-Patchwork-Id: 9242385 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B01F860756 for ; Thu, 21 Jul 2016 19:24:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9DDA227C0B for ; Thu, 21 Jul 2016 19:24:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 929A927DE0; Thu, 21 Jul 2016 19:24:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 215D527C0B for ; Thu, 21 Jul 2016 19:24:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E1B166EA34; Thu, 21 Jul 2016 19:24:37 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by gabe.freedesktop.org (Postfix) with ESMTPS id D8A946EA32; Thu, 21 Jul 2016 19:24:14 +0000 (UTC) Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7D1B7C05AA59; Thu, 21 Jul 2016 19:24:14 +0000 (UTC) Received: from ecstaticemu.bos.redhat.com (dhcp-25-142.bos.redhat.com [10.18.25.142]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u6LJO92Q023883; Thu, 21 Jul 2016 15:24:13 -0400 From: Lyude To: intel-gfx@lists.freedesktop.org, Matt Roper Subject: [PATCH v2 2/4] drm/i915/skl: Only flush pipes when we change the ddb allocation Date: Thu, 21 Jul 2016 15:23:38 -0400 Message-Id: <1469129020-2680-3-git-send-email-cpaul@redhat.com> In-Reply-To: <1469129020-2680-1-git-send-email-cpaul@redhat.com> References: <1469129020-2680-1-git-send-email-cpaul@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Thu, 21 Jul 2016 19:24:14 +0000 (UTC) Cc: Radhakrishna Sripada , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Hans de Goede , Daniel Vetter , Lyude X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Manual pipe flushes are only necessary in order to make sure that we prevent pipes with changed ddb allocations from overlapping from one another at any point in time. Additionally, forcing us to wait for the next vblank every time we have to update the watermark values because the cursor was moving between screens will introduce a rather noticable lag for users. Signed-off-by: Lyude Cc: stable@vger.kernel.org Cc: Ville Syrjälä Cc: Daniel Vetter Cc: Radhakrishna Sripada Cc: Hans de Goede Cc: Matt Roper --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 31 +++++++++++++++++++++++++++++-- 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c97724d..9e1e045 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1597,6 +1597,7 @@ struct skl_ddb_allocation { struct skl_wm_values { unsigned dirty_pipes; + bool ddb_changed; struct skl_ddb_allocation ddb; uint32_t wm_linetime[I915_MAX_PIPES]; uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 56ddd71..55237ea 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3789,6 +3789,12 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv, new_ddb = &new_values->ddb; cur_ddb = &dev_priv->wm.skl_hw.ddb; + /* We only ever need to flush when the ddb allocations change */ + if (!new_values->ddb_changed) + return; + + new_values->ddb_changed = false; + /* * First pass: flush the pipes with the new allocation contained into * the old space. @@ -3893,6 +3899,22 @@ pipes_modified(struct drm_atomic_state *state) return ret; } +static bool +skl_pipe_ddb_changed(struct skl_ddb_allocation *old, + struct skl_ddb_allocation *new, + enum pipe pipe) +{ + if (memcmp(&old->pipe[pipe], &new->pipe[pipe], + sizeof(old->pipe[pipe])) != 0 || + memcmp(&old->plane[pipe], &new->plane[pipe], + sizeof(old->plane[pipe])) != 0 || + memcmp(&old->y_plane[pipe], &new->y_plane[pipe], + sizeof(old->y_plane[pipe])) != 0) + return true; + + return false; +} + static int skl_compute_ddb(struct drm_atomic_state *state) { @@ -3900,7 +3922,8 @@ skl_compute_ddb(struct drm_atomic_state *state) struct drm_i915_private *dev_priv = to_i915(dev); struct intel_atomic_state *intel_state = to_intel_atomic_state(state); struct intel_crtc *intel_crtc; - struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb; + struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb; + struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb; uint32_t realloc_pipes = pipes_modified(state); int ret; @@ -3938,9 +3961,13 @@ skl_compute_ddb(struct drm_atomic_state *state) if (IS_ERR(cstate)) return PTR_ERR(cstate); - ret = skl_allocate_pipe_ddb(cstate, ddb); + ret = skl_allocate_pipe_ddb(cstate, new_ddb); if (ret) return ret; + + if (!intel_state->wm_results.ddb_changed && + skl_pipe_ddb_changed(old_ddb, new_ddb, intel_crtc->pipe)) + intel_state->wm_results.ddb_changed = true; } return 0;