From patchwork Mon Aug 22 03:36:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: huang lin X-Patchwork-Id: 9293133 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 483FE60574 for ; Mon, 22 Aug 2016 08:09:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 390A928859 for ; Mon, 22 Aug 2016 08:09:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2D3342887A; Mon, 22 Aug 2016 08:09:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CC16F28859 for ; Mon, 22 Aug 2016 08:09:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 135D66E3C3; Mon, 22 Aug 2016 08:09:15 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pa0-f65.google.com (mail-pa0-f65.google.com [209.85.220.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2F2736E1CC for ; Mon, 22 Aug 2016 03:36:41 +0000 (UTC) Received: by mail-pa0-f65.google.com with SMTP id cf3so7217840pad.2 for ; Sun, 21 Aug 2016 20:36:41 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fFogyKOgx2viKsG3690mSsdFXjRm1xld4h1MPdLUE+U=; b=iwBEF7ZMnMnifQb+qYPqQhkUc9snpxvnzAb/prZXsHNuGQ652vZYHrwAxDg2MGQ7/V tGJ7tWb2aIq2hnLsMnWPv/xKNcBCjkY90dgheopvkl+JUn4aE0F3UIh2mrBFFN9CXF86 0vtukr07YzZITZovJs4yLNm46376wOQkP1oJACXi8q9HWJ0j3UpreTNocVYe2zUrXhi3 cuA/sFxZj7VM1c50WuUPC2X2qItey9sXJdOpYZNrXeXf8gvImAemRliJBtQPiXipV90I u4PwNaPvrtC5dt+yiE6k/63eKoxVLCTRVN+IuMQb8+u1HFgMBBUWtkUDyXxggSIAM+Tw 6iYg== X-Gm-Message-State: AEkooutdJHCtlETgde+qs3G+RdNcKK1uYNpugq1mj1Vds0PdA0sg3X7cDbMHaKSlcsydsw== X-Received: by 10.66.127.38 with SMTP id nd6mr38237369pab.74.1471837000805; Sun, 21 Aug 2016 20:36:40 -0700 (PDT) Received: from hl-ThinkPad-X240.corp.google.com ([172.22.52.149]) by smtp.gmail.com with ESMTPSA id a20sm23063699pfa.27.2016.08.21.20.36.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 21 Aug 2016 20:36:40 -0700 (PDT) From: Lin Huang To: heiko@sntech.de, myungjoo.ham@samsung.com Subject: [PATCH v7 3/8] clk: rockchip: rk3399: add ddrc clock support Date: Mon, 22 Aug 2016 11:36:19 +0800 Message-Id: <1471836984-6316-4-git-send-email-hl@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1471836984-6316-1-git-send-email-hl@rock-chips.com> References: <1471836984-6316-1-git-send-email-hl@rock-chips.com> X-Mailman-Approved-At: Mon, 22 Aug 2016 08:09:13 +0000 Cc: tixy@linaro.org, mark.rutland@arm.com, dbasehore@chromium.org, Lin Huang , cw00.choi@samsung.com, mturquette@baylibre.com, typ@rock-chips.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, kyungmin.park@samsung.com, sudeep.holla@arm.com, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP add ddrc clock setting, so we can do ddr frequency scaling on rk3399 platform in future. Signed-off-by: Lin Huang --- Changes in v7: - change SCLK_DDRC name from clk_ddrc to sclk_ddrc Changes in v6: - None Changes in v5: - fit for the ddr type Changes in v4: - None Changes in v3: - None Changes in v2: - remove clk_ddrc_dpll_src from critical clock list Changes in v1: - remove ddrc source CLK_IGNORE_UNUSED flag - move clk_ddrc and clk_ddrc_dpll_src to critical drivers/clk/rockchip/clk-rk3399.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c index e445cd6..134bd18 100644 --- a/drivers/clk/rockchip/clk-rk3399.c +++ b/drivers/clk/rockchip/clk-rk3399.c @@ -120,6 +120,10 @@ PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src", "clk_core_b_bpll_src", "clk_core_b_dpll_src", "clk_core_b_gpll_src" }; +PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src", + "clk_ddrc_bpll_src", + "clk_ddrc_dpll_src", + "clk_ddrc_gpll_src" }; PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src", "gpll_aclk_cci_src", "npll_aclk_cci_src", @@ -1379,6 +1383,18 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = { COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED, RK3368_CLKSEL_CON(58), 0, 5, DFLAGS, RK3368_CLKGATE_CON(13), 11, GFLAGS), + + /* ddrc */ + GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3), + 0, GFLAGS), + GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3), + 1, GFLAGS), + GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3), + 2, GFLAGS), + GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3), + 3, GFLAGS), + COMPOSITE_DDRCLK(SCLK_DDRC, "sclk_ddrc", mux_ddrclk_p, 0, + RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP), }; static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = { @@ -1493,6 +1509,9 @@ static const char *const rk3399_cru_critical_clocks[] __initconst = { "gpll_aclk_perilp0_src", "gpll_aclk_perihp_src", "aclk_vio_noc", + + /* ddrc */ + "sclk_ddrc" }; static const char *const rk3399_pmucru_critical_clocks[] __initconst = {