From patchwork Mon Aug 22 03:36:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: huang lin X-Patchwork-Id: 9293139 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6418A60574 for ; Mon, 22 Aug 2016 08:09:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5524328879 for ; Mon, 22 Aug 2016 08:09:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 49D632887E; Mon, 22 Aug 2016 08:09:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id F0C6228879 for ; Mon, 22 Aug 2016 08:09:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 83C8B6E3DC; Mon, 22 Aug 2016 08:09:30 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pf0-f194.google.com (mail-pf0-f194.google.com [209.85.192.194]) by gabe.freedesktop.org (Postfix) with ESMTPS id 80A0D6E2BD for ; Mon, 22 Aug 2016 03:36:44 +0000 (UTC) Received: by mail-pf0-f194.google.com with SMTP id h186so5461025pfg.2 for ; Sun, 21 Aug 2016 20:36:44 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NZLSSxiv7s84JorkQX4HbM5Sf5Ie7jECbknWoHWoy90=; b=A46hcMDk11uwsMBj7BtydvmjiSf/s09C2FTYiEsE+NYFDX1GTK2UkvDiGpR4zX1Lw6 CGkrJzaehddGRklf2dJAU0ZHLb1mjjzw23WFO+Tk+OE4LbINUwkte2qiPagwV6O6RKqT 93MiqVasE6WHSkYifr9xHGLFdYRzZ08/opGr51dUxmrMRS73kC3G0Xr1/gUHzHuaslCm ZJPwesQ/+F7DpkaAfD3/MaIxROcd23y9jO6F6Onu8BJZcKYI8ACEqi4dbVKdfplJs7Mq ToAKEmFzf/TENFeW1ZziwO+Ln4PKNqTwa1PqHfbXIXz3tbYGqBhD1fGecc+NOisAICFC 3SKQ== X-Gm-Message-State: AEkooutpXgg/K2oL+d3XNe5tiTxUcpjj20V/olOCaeHJm5pdyKNXaiBXWALbESN9oQ6Enw== X-Received: by 10.98.152.129 with SMTP id d1mr39076031pfk.126.1471837004128; Sun, 21 Aug 2016 20:36:44 -0700 (PDT) Received: from hl-ThinkPad-X240.corp.google.com ([172.22.52.149]) by smtp.gmail.com with ESMTPSA id a20sm23063699pfa.27.2016.08.21.20.36.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 21 Aug 2016 20:36:43 -0700 (PDT) From: Lin Huang To: heiko@sntech.de, myungjoo.ham@samsung.com Subject: [PATCH v7 6/8] Documentation: bindings: add dt documentation for rk3399 dmc Date: Mon, 22 Aug 2016 11:36:22 +0800 Message-Id: <1471836984-6316-7-git-send-email-hl@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1471836984-6316-1-git-send-email-hl@rock-chips.com> References: <1471836984-6316-1-git-send-email-hl@rock-chips.com> X-Mailman-Approved-At: Mon, 22 Aug 2016 08:09:13 +0000 Cc: tixy@linaro.org, mark.rutland@arm.com, dbasehore@chromium.org, Lin Huang , cw00.choi@samsung.com, mturquette@baylibre.com, typ@rock-chips.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, kyungmin.park@samsung.com, sudeep.holla@arm.com, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the documentation for rockchip rk3399 dmc driver. Signed-off-by: Lin Huang --- Changes in v7: -None Changes in v6: -Add more detail in Documentation Changes in v5: -None Changes in v4: -None Changes in v3: -None Changes in v2: -None Changes in v1: -None .../devicetree/bindings/devfreq/rk3399_dmc.txt | 85 ++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt new file mode 100644 index 0000000..b787abb --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt @@ -0,0 +1,85 @@ +* Rockchip rk3399 DMC(Dynamic Memory Controller) device + +Required properties: +- compatible: Must be "rockchip,rk3399-dmc". +- devfreq-events: Node to get DDR loading, Refer to + Documentation/devicetree/bindings/devfreq/rockchip-dfi.txt +- interrupts: The interrupt number to the CPU. The interrupt specifier format + depends on the interrupt controller. It should be DCF interrupts, + when DDR dvfs finish, it will happen. +- clocks: Phandles for clock specified in "clock-names" property +- clock-names : The name of clock used by the DFI, must be "pclk_ddr_mon"; +- operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt + for details. +- center-supply: DMC supply node. +- status: Marks the node enabled/disabled. + +Optional properties: +- ddr_timing: DDR timing need to pass to arm trust firmware +- upthreshold: The upthreshold to simpleondeamnd policy +- downdifferential: The downdifferential to simpleondeamnd policy + +Example: + + ddr_timing: ddr_timing { + compatible = "rockchip,ddr-timing"; + ddr3_speed_bin = <21>; + pd_idle = <0>; + sr_idle = <0>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + dram_dll_dis_freq = <300>; + phy_dll_dis_freq = <125>; + + ddr3_odt_dis_freq = <333>; + ddr3_drv = ; + ddr3_odt = ; + phy_ddr3_ca_drv = ; + phy_ddr3_dq_drv = ; + phy_ddr3_odt = ; + + lpddr3_odt_dis_freq = <333>; + lpddr3_drv = ; + lpddr3_odt = ; + phy_lpddr3_ca_drv = ; + phy_lpddr3_dq_drv = ; + phy_lpddr3_odt = ; + + lpddr4_odt_dis_freq = <333>; + lpddr4_drv = ; + lpddr4_dq_odt = ; + lpddr4_ca_odt = ; + phy_lpddr4_ca_drv = ; + phy_lpddr4_ck_cs_drv = ; + phy_lpddr4_dq_drv = ; + phy_lpddr4_odt = ; + }; + + dmc_opp_table: dmc_opp_table { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + }; + + dmc: dmc { + compatible = "rockchip,rk3399-dmc"; + devfreq-events = <&dfi>; + interrupts = ; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + ddr_timing = <&ddr_timing>; + operating-points-v2 = <&dmc_opp_table>; + center-supply = <&ppvar_centerlogic>; + upthreshold = <15>; + downdifferential = <10>; + status = "disabled"; + }; +