| Message ID | 1471863672-7104-17-git-send-email-l.stach@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
2016-08-22 13:01 GMT+02:00 Lucas Stach <l.stach@pengutronix.de>: > Bit 30 of the interrupt status signals an MMU exception. Handle this > condition properly and dump some useful registers. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 12 ++++++++++++ > drivers/gpu/drm/etnaviv/state_hi.xml.h | 9 +++++---- > 2 files changed, 17 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c > index 4c706438c7c8..923f6c78e1af 100644 > --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c > +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c > @@ -1402,6 +1402,18 @@ static irqreturn_t irq_handler(int irq, void *data) > intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; > } > > + if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { > + int i; > + > + dev_err(gpu->dev, "MMU fault status 0x%08x\n", > + gpu_read(gpu, VIVS_MMUv2_STATUS)); > + for (i = 0; i < 4; i++) > + dev_err(gpu->dev, "MMU %d fault addr 0x%08x\n", > + i, gpu_read(gpu, > + VIVS_MMUv2_EXCEPTION_ADDR(i))); > + intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; > + } > + > while ((event = ffs(intr)) != 0) { > struct fence *fence; > > diff --git a/drivers/gpu/drm/etnaviv/state_hi.xml.h b/drivers/gpu/drm/etnaviv/state_hi.xml.h > index 807a3d9e0dd5..43c73e2ed34f 100644 > --- a/drivers/gpu/drm/etnaviv/state_hi.xml.h > +++ b/drivers/gpu/drm/etnaviv/state_hi.xml.h > @@ -8,10 +8,10 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng > git clone git://0x04.net/rules-ng-ng > > The rules-ng-ng source files this header was generated from are: > -- state_hi.xml ( 24309 bytes, from 2015-12-12 09:02:53) > -- common.xml ( 18437 bytes, from 2015-12-12 09:02:53) > +- state_hi.xml ( 25620 bytes, from 2016-08-19 22:07:37) > +- common.xml ( 20583 bytes, from 2016-06-07 05:22:38) > > -Copyright (C) 2015 > +Copyright (C) 2016 > */ > > > @@ -78,9 +78,10 @@ Copyright (C) 2015 > #define VIVS_HI_AXI_STATUS_DET_RD_ERR 0x00000200 > > #define VIVS_HI_INTR_ACKNOWLEDGE 0x00000010 > -#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x7fffffff > +#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x3fffffff > #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT 0 > #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x) (((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK) > +#define VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION 0x40000000 > #define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR 0x80000000 > > #define VIVS_HI_INTR_ENBL 0x00000014 Where can I find the rnndb patch? Just share it and I will take care that it gets integrated. greets -- Christian Gmeiner, MSc https://soundcloud.com/christian-gmeiner
Hi Christian, Am Dienstag, den 23.08.2016, 11:58 +0200 schrieb Christian Gmeiner: > 2016-08-22 13:01 GMT+02:00 Lucas Stach <l.stach@pengutronix.de>: > > Bit 30 of the interrupt status signals an MMU exception. Handle this > > condition properly and dump some useful registers. > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > --- [...] > > > > > > @@ -78,9 +78,10 @@ Copyright (C) 2015 > > #define VIVS_HI_AXI_STATUS_DET_RD_ERR 0x00000200 > > > > #define VIVS_HI_INTR_ACKNOWLEDGE 0x00000010 > > -#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x7fffffff > > +#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x3fffffff > > #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT 0 > > #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x) (((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK) > > +#define VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION 0x40000000 > > #define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR 0x80000000 > > > > #define VIVS_HI_INTR_ENBL 0x00000014 > > Where can I find the rnndb patch? Just share it and I will take care > that it gets integrated. > Sorry about that. It's still on my machine at home. Will post it in the evening. Regards, Lucas
On Mon, Aug 22, 2016 at 7:01 AM, Lucas Stach <l.stach@pengutronix.de> wrote: > Bit 30 of the interrupt status signals an MMU exception. Handle this > condition properly and dump some useful registers. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 12 ++++++++++++ > drivers/gpu/drm/etnaviv/state_hi.xml.h | 9 +++++---- > 2 files changed, 17 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c > index 4c706438c7c8..923f6c78e1af 100644 > --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c > +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c > @@ -1402,6 +1402,18 @@ static irqreturn_t irq_handler(int irq, void *data) > intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; > } > > + if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { > + int i; > + > + dev_err(gpu->dev, "MMU fault status 0x%08x\n", > + gpu_read(gpu, VIVS_MMUv2_STATUS)); Drive-by comment, and I don't know if this is the case w/ vivante, but on adreno I have observed that when I get iommu faults (for example, bad texture state or something like that) I tend to get a *lot* of iommu faults, not just one. If that is the case here, you might want to ratelimit the dev_err prints.. BR, -R > + for (i = 0; i < 4; i++) > + dev_err(gpu->dev, "MMU %d fault addr 0x%08x\n", > + i, gpu_read(gpu, > + VIVS_MMUv2_EXCEPTION_ADDR(i))); > + intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; > + } > + > while ((event = ffs(intr)) != 0) { > struct fence *fence; > > diff --git a/drivers/gpu/drm/etnaviv/state_hi.xml.h b/drivers/gpu/drm/etnaviv/state_hi.xml.h > index 807a3d9e0dd5..43c73e2ed34f 100644 > --- a/drivers/gpu/drm/etnaviv/state_hi.xml.h > +++ b/drivers/gpu/drm/etnaviv/state_hi.xml.h > @@ -8,10 +8,10 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng > git clone git://0x04.net/rules-ng-ng > > The rules-ng-ng source files this header was generated from are: > -- state_hi.xml ( 24309 bytes, from 2015-12-12 09:02:53) > -- common.xml ( 18437 bytes, from 2015-12-12 09:02:53) > +- state_hi.xml ( 25620 bytes, from 2016-08-19 22:07:37) > +- common.xml ( 20583 bytes, from 2016-06-07 05:22:38) > > -Copyright (C) 2015 > +Copyright (C) 2016 > */ > > > @@ -78,9 +78,10 @@ Copyright (C) 2015 > #define VIVS_HI_AXI_STATUS_DET_RD_ERR 0x00000200 > > #define VIVS_HI_INTR_ACKNOWLEDGE 0x00000010 > -#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x7fffffff > +#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x3fffffff > #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT 0 > #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x) (((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK) > +#define VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION 0x40000000 > #define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR 0x80000000 > > #define VIVS_HI_INTR_ENBL 0x00000014 > -- > 2.8.1 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index 4c706438c7c8..923f6c78e1af 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1402,6 +1402,18 @@ static irqreturn_t irq_handler(int irq, void *data) intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR; } + if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) { + int i; + + dev_err(gpu->dev, "MMU fault status 0x%08x\n", + gpu_read(gpu, VIVS_MMUv2_STATUS)); + for (i = 0; i < 4; i++) + dev_err(gpu->dev, "MMU %d fault addr 0x%08x\n", + i, gpu_read(gpu, + VIVS_MMUv2_EXCEPTION_ADDR(i))); + intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION; + } + while ((event = ffs(intr)) != 0) { struct fence *fence; diff --git a/drivers/gpu/drm/etnaviv/state_hi.xml.h b/drivers/gpu/drm/etnaviv/state_hi.xml.h index 807a3d9e0dd5..43c73e2ed34f 100644 --- a/drivers/gpu/drm/etnaviv/state_hi.xml.h +++ b/drivers/gpu/drm/etnaviv/state_hi.xml.h @@ -8,10 +8,10 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- state_hi.xml ( 24309 bytes, from 2015-12-12 09:02:53) -- common.xml ( 18437 bytes, from 2015-12-12 09:02:53) +- state_hi.xml ( 25620 bytes, from 2016-08-19 22:07:37) +- common.xml ( 20583 bytes, from 2016-06-07 05:22:38) -Copyright (C) 2015 +Copyright (C) 2016 */ @@ -78,9 +78,10 @@ Copyright (C) 2015 #define VIVS_HI_AXI_STATUS_DET_RD_ERR 0x00000200 #define VIVS_HI_INTR_ACKNOWLEDGE 0x00000010 -#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x7fffffff +#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x3fffffff #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT 0 #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x) (((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK) +#define VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION 0x40000000 #define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR 0x80000000 #define VIVS_HI_INTR_ENBL 0x00000014
Bit 30 of the interrupt status signals an MMU exception. Handle this condition properly and dump some useful registers. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 12 ++++++++++++ drivers/gpu/drm/etnaviv/state_hi.xml.h | 9 +++++---- 2 files changed, 17 insertions(+), 4 deletions(-)