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Fri, 23 Sep 2016 11:43:39 +0100 (BST) Received: from eusmgms2.samsung.com (unknown [182.198.249.180]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20160923104338eucas1p11e63c7ef693d7b495872fbc2661d0e12~27dLvY7HM1107511075eucas1p1G; Fri, 23 Sep 2016 10:43:38 +0000 (GMT) X-AuditID: cbfec7ef-f79e76d000005b57-73-57e5075b745b Received: from eusync2.samsung.com ( [203.254.199.212]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id FF.5A.10494.D2705E75; Fri, 23 Sep 2016 11:42:53 +0100 (BST) Received: from AMDC2768.digital.local ([106.116.147.88]) by eusync2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0ODY00EQ6DSPIKB0@eusync2.samsung.com>; Fri, 23 Sep 2016 11:43:37 +0100 (BST) From: Andrzej Hajda To: Inki Dae Subject: [PATCH] drm/exynos/fimd: add clock rate checking Date: Fri, 23 Sep 2016 12:43:29 +0200 Message-id: <1474627409-28711-1-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 2.7.4 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrOIsWRmVeSWpSXmKPExsWy7djP87rR7E/DDV7s5LO4te4cq8XGGetZ La58fc9mMen+BBaLGef3MVmsPXKX3aJt9QdWB3aP+93HmTz+HWP36NuyitHj8ya5AJYoLpuU 1JzMstQifbsEroxHD+4yFTTIVHx8sJGpgfGfWBcjJ4eEgInEzMv32CBsMYkL99YD2VwcQgLL GCVOfDzJAuF8ZpSY/28uO0zHuWcPmeGq5rw6AlXVwCQx6/ElRpAqNgFNib+bb4LNFRFQlli1 r50dpIhZoJlJ4sj+VWCjhAUsJWY/uQE0ioODRUBVovtRHUiYV8BZYuesfqib5CRunusE2yYh cJlNYsOWKywg9RICshKbDjBD1LhIrO1ZDVUvLPHq+BaoS2UkLk/uZoHo7WaU+NR/gh3CmcIo 8e/DDKhua4nDxy+ygtjMAnwSk7ZNZ4ZYwCvR0SYEUeIh8e7qT1YI21Hiw5MesBuEBGIlrnyW ncAovYCRYRWjSGppcW56arGhXnFibnFpXrpecn7uJkZgdJ7+d/z9DsanzSGHGAU4GJV4eB88 fhwuxJpYVlyZe4hRgoNZSYQ3i+VpuBBvSmJlVWpRfnxRaU5q8SFGaQ4WJXHevQuuhAsJpCeW pGanphakFsFkmTg4pRoYi/dff8KtmC4dsjTRheH+nz0+9ZEv00TkchaILasV5ZwoaLAsUELk 5Hpfj7ozz1TuC3keFv/akfQ9PYLr4d0rbmcZtH/FP74mLPIgyXx39OvSTeF+9c/PcizaPJf/ /ZQ0vxvBO04sWDz9yISfk3s5cq4feL/smZ743E0XD7RvDd1Qt9WkkFE6VomlOCPRUIu5qDgR AGzOug7KAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrNLMWRmVeSWpSXmKPExsVy+t/xK7q67E/DDZbN4ra4te4cq8XGGetZ La58fc9mMen+BBaLGef3MVmsPXKX3aJt9QdWB3aP+93HmTz+HWP36NuyitHj8ya5AJYoN5uM 1MSU1CKF1Lzk/JTMvHRbpdAQN10LJYW8xNxUW6UIXd+QICWFssScUiDPyAANODgHuAcr6dsl uGU8enCXqaBBpuLjg41MDYz/xLoYOTkkBEwkzj17yAxhi0lcuLeerYuRi0NIYAmjxOL7h1gg nCYmiV93L7GAVLEJaEr83XyTDcQWEVCWWLWvnR2kiFmglUli/an5rCAJYQFLidlPbgCN5eBg EVCV6H5UBxLmFXCW2Dmrnw1im5zEzXOdzBMYuRcwMqxiFEktLc5Nzy020itOzC0uzUvXS87P 3cQIDMhtx35u2cHY9S74EKMAB6MSD++Dx4/DhVgTy4orcw8xSnAwK4nwZrE8DRfiTUmsrEot yo8vKs1JLT7EaAq0eyKzlGhyPjBa8kriDU0MzS0NjYwtLMyNjJTEead+uBIuJJCeWJKanZpa kFoE08fEwSnVwJhmectcV9m9bG+cTpHf/zV7ehZ+3FLF5/m1QXdJaoYE30nZVrXN/P0nVY1f vNB3uaJ87MB9TWG3whdcS6Lcf+3zE6za2Cn8tnkFhzSLpnlmYNExKUF93qSfU6uf8DS26rne fBB/a/9+L67NR1sy3hpbpOStP57JWfYmTmavyrRbNa53/siFKLEUZyQaajEXFScCAPPd/kBe AgAA X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20160923104338eucas1p11e63c7ef693d7b495872fbc2661d0e12 X-Msg-Generator: CA X-Sender-IP: 182.198.249.180 X-Local-Sender: =?UTF-8?B?QW5kcnplaiBIYWpkYRtTUlBPTC1LZXJuZWwgKFRQKRvsgrw=?= =?UTF-8?B?7ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?QW5kcnplaiBIYWpkYRtTUlBPTC1LZXJuZWwgKFRQKRtTYW1z?= =?UTF-8?B?dW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20160923104338eucas1p11e63c7ef693d7b495872fbc2661d0e12 X-RootMTR: 20160923104338eucas1p11e63c7ef693d7b495872fbc2661d0e12 References: Cc: linux-samsung-soc@vger.kernel.org, Bartlomiej Zolnierkiewicz , dri-devel@lists.freedesktop.org, Tobias Jakobi , Marek Szyprowski X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP In case of some platforms fimd clocks can be configured to very low values, as a result refresh rate can be very low and driver/drm-core will timeout waiting for vblanks, it will result in premature removal of framebuffers and will cause oopses. The patch adds atomic_check callback to fimd to prevent setting such modes. Reported-by: Tobias Jakobi Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 41 ++++++++++++++++++++++---------- 1 file changed, 29 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index d472164..0e74999 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -198,6 +198,7 @@ struct fimd_context { atomic_t wait_vsync_event; atomic_t win_updated; atomic_t triggering; + int clkdiv; const struct fimd_driver_data *driver_data; struct drm_encoder *encoder; @@ -389,15 +390,18 @@ static void fimd_clear_channels(struct exynos_drm_crtc *crtc) pm_runtime_put(ctx->dev); } -static u32 fimd_calc_clkdiv(struct fimd_context *ctx, - const struct drm_display_mode *mode) + +static int fimd_atomic_check(struct exynos_drm_crtc *crtc, + struct drm_crtc_state *state) { - unsigned long ideal_clk; - u32 clkdiv; + struct drm_display_mode *mode = &state->adjusted_mode; + struct fimd_context *ctx = crtc->ctx; + unsigned long ideal_clk, lcd_rate; + int clkdiv; if (mode->clock == 0) { - DRM_ERROR("Mode has zero clock value.\n"); - return 0xff; + DRM_INFO("Mode has zero clock value.\n"); + return -EINVAL; } ideal_clk = mode->clock * 1000; @@ -410,10 +414,23 @@ static u32 fimd_calc_clkdiv(struct fimd_context *ctx, ideal_clk *= 2; } + lcd_rate = clk_get_rate(ctx->lcd_clk); + if (2 * lcd_rate < ideal_clk) { + DRM_INFO("sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n", + lcd_rate, ideal_clk); + return -EINVAL; + } + /* Find the clock divider value that gets us closest to ideal_clk */ - clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(ctx->lcd_clk), ideal_clk); + clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk); + if (clkdiv >= 0x200) { + DRM_INFO("requested pixel clock(%lu) too low\n", ideal_clk); + return -EINVAL; + } + + ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff; - return (clkdiv < 0x100) ? clkdiv : 0xff; + return 0; } static void fimd_setup_trigger(struct fimd_context *ctx) @@ -442,7 +459,7 @@ static void fimd_commit(struct exynos_drm_crtc *crtc) struct drm_display_mode *mode = &crtc->base.state->adjusted_mode; const struct fimd_driver_data *driver_data = ctx->driver_data; void *timing_base = ctx->regs + driver_data->timing_base; - u32 val, clkdiv; + u32 val; if (ctx->suspended) return; @@ -543,9 +560,8 @@ static void fimd_commit(struct exynos_drm_crtc *crtc) if (ctx->driver_data->has_clksel) val |= VIDCON0_CLKSEL_LCD; - clkdiv = fimd_calc_clkdiv(ctx, mode); - if (clkdiv > 1) - val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; + if (ctx->clkdiv > 1) + val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; writel(val, ctx->regs + VIDCON0); } @@ -939,6 +955,7 @@ static const struct exynos_drm_crtc_ops fimd_crtc_ops = { .update_plane = fimd_update_plane, .disable_plane = fimd_disable_plane, .atomic_flush = fimd_atomic_flush, + .atomic_check = fimd_atomic_check, .te_handler = fimd_te_handler, };