From patchwork Tue Dec 20 13:47:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sharma, Shashank" X-Patchwork-Id: 9481563 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0BC7660237 for ; Tue, 20 Dec 2016 13:36:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F0841284D5 for ; Tue, 20 Dec 2016 13:36:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E5895284E6; Tue, 20 Dec 2016 13:36:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0F905284D5 for ; Tue, 20 Dec 2016 13:36:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1114E6E1D0; Tue, 20 Dec 2016 13:36:52 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id EBE1A6EE40; Tue, 20 Dec 2016 13:36:34 +0000 (UTC) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP; 20 Dec 2016 05:36:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,378,1477983600"; d="scan'208";a="44925117" Received: from shashanks-desktop.iind.intel.com ([10.223.26.24]) by fmsmga005.fm.intel.com with ESMTP; 20 Dec 2016 05:36:32 -0800 From: Shashank Sharma To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v2 2/2] drm: parse hf-vsdb Date: Tue, 20 Dec 2016 19:17:30 +0530 Message-Id: <1482241650-14435-2-git-send-email-shashank.sharma@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1482241650-14435-1-git-send-email-shashank.sharma@intel.com> References: <1482241650-14435-1-git-send-email-shashank.sharma@intel.com> Cc: Daniel Vetter , Thierry Reding , Jose Abreu X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP HDMI 2.0 / CEA-861-F specs define a new CEA extension data block, called hdmi-forum vendor specific data block (HF-VSDB). This block contains information about sink's support for HDMI 2.0 compliant features. These features are: - Deep color YUV 420 support and BPC - 3D flags for - OSD Displarity - Dual view signaling - independent view signaling - SCDC support - Max TMDS char rate - Scrambling support This patch adds a parser function for this block, and add flags to indicate support for new features, in drm_display_info structure V2: - Addressed review comments from Thierry - remove len > 31 check - remove version check - fix duplicate values for macros of 36 and 30-bit depths - Added a sub-class for HDMI related information within drm_display_info (Thierry, Daniel) and populated it with HF-VSDB specific info. Cc: Thierry Reding Cc: Daniel Vetter Cc: Jose Abreu Signed-off-by: Shashank Sharma --- drivers/gpu/drm/drm_edid.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++ include/drm/drm_edid.h | 5 ++++ include/linux/hdmi.h | 1 + 3 files changed, 76 insertions(+) diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index b552197..59e04fb 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -3224,6 +3224,23 @@ static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, return 0; } +static bool cea_db_is_hf_vsdb(const u8 *db) +{ + u8 len; + int hfvsdb_id; + + if (cea_db_tag(db) != VENDOR_BLOCK) + return false; + + len = cea_db_payload_len(db); + if (len < 7) + return false; + + hfvsdb_id = db[1] | (db[2] << 8) | (db[3] << 16); + + return hfvsdb_id == HDMI_IEEE_OUI_HFVSDB; +} + static bool cea_db_is_hdmi_vsdb(const u8 *db) { int hdmi_id; @@ -3768,6 +3785,57 @@ bool drm_rgb_quant_range_selectable(struct edid *edid) } EXPORT_SYMBOL(drm_rgb_quant_range_selectable); +static void drm_parse_yuv420_deep_color_info(struct drm_connector *connector, + const u8 *db) +{ + struct drm_hdmi_info *info = &connector->display_info.hdmi_info; + + if (db[7] & DRM_EDID_YUV420_DC_48) + info->edid_yuv420_dc_modes |= DRM_EDID_YUV420_DC_48; + if (db[7] & DRM_EDID_YUV420_DC_36) + info->edid_yuv420_dc_modes |= DRM_EDID_YUV420_DC_36; + if (db[7] & DRM_EDID_YUV420_DC_30) + info->edid_yuv420_dc_modes |= DRM_EDID_YUV420_DC_30; + + if (!info->edid_yuv420_dc_modes) { + DRM_DEBUG("%s: No YUV 420 deep color support in sink.\n", + connector->name); + return; + } +} + +static void +drm_parse_hf_vsdb(struct drm_connector *connector, const u8 *db) +{ + struct drm_display_info *info = &connector->display_info; + struct drm_hdmi_info *hdmi_info = &info->hdmi_info; + + if (db[5]) { + /* + * If the sink supplies max tmds char rate in db, + * the actual max tmds rate = db[5] * 5Mhz. + */ + info->max_tmds_clock = db[5] * 5000; + DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", + info->max_tmds_clock); + } + + if (db[6] & DRM_HFVSDB_SCDC_SUPPORT) + hdmi_info->scdc_supported = true; + if (db[6] & DRM_HFVSDB_SCDC_RR_CAP) + hdmi_info->scdc_rr_cap = true; + if (db[6] & DRM_HFVSDB_SCRAMBLING) + hdmi_info->scrambling = true; + if (db[6] & DRM_HFVSDB_INDEPENDENT_VIEW) + hdmi_info->independent_view_3d = true; + if (db[6] & DRM_HFVSDB_DUAL_VIEW) + hdmi_info->dual_view_3d = true; + if (db[6] & DRM_HFVSDB_3D_OSD) + hdmi_info->osd_disparity_3d = true; + + drm_parse_yuv420_deep_color_info(connector, db); +} + static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, const u8 *hdmi) { @@ -3882,6 +3950,8 @@ static void drm_parse_cea_ext(struct drm_connector *connector, if (cea_db_is_hdmi_vsdb(db)) drm_parse_hdmi_vsdb_video(connector, db); + if (cea_db_is_hf_vsdb(db)) + drm_parse_hf_vsdb(connector, db); } } diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index 38eabf6..df606e3 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h @@ -212,6 +212,11 @@ struct detailed_timing { #define DRM_EDID_HDMI_DC_30 (1 << 4) #define DRM_EDID_HDMI_DC_Y444 (1 << 3) +/* YUV 420 deep color modes */ +#define DRM_EDID_YUV420_DC_48 (1 << 6) +#define DRM_EDID_YUV420_DC_36 (1 << 5) +#define DRM_EDID_YUV420_DC_30 (1 << 4) + /* ELD Header Block */ #define DRM_ELD_HEADER_BLOCK_SIZE 4 diff --git a/include/linux/hdmi.h b/include/linux/hdmi.h index edbb4fc..2d4e9ef 100644 --- a/include/linux/hdmi.h +++ b/include/linux/hdmi.h @@ -35,6 +35,7 @@ enum hdmi_infoframe_type { }; #define HDMI_IEEE_OUI 0x000c03 +#define HDMI_IEEE_OUI_HFVSDB 0xC45DD8 #define HDMI_INFOFRAME_HEADER_SIZE 4 #define HDMI_AVI_INFOFRAME_SIZE 13 #define HDMI_SPD_INFOFRAME_SIZE 25