From patchwork Wed Dec 21 15:29:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sharma, Shashank" X-Patchwork-Id: 9483183 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5EA2260772 for ; Wed, 21 Dec 2016 15:18:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4EE6F283FC for ; Wed, 21 Dec 2016 15:18:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 437582841D; Wed, 21 Dec 2016 15:18:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B5576283FC for ; Wed, 21 Dec 2016 15:18:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C6A56EC22; Wed, 21 Dec 2016 15:18:09 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id AED126EC22; Wed, 21 Dec 2016 15:18:07 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga104.jf.intel.com with ESMTP; 21 Dec 2016 07:18:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,384,1477983600"; d="scan'208";a="205377067" Received: from shashanks-desktop.iind.intel.com ([10.223.26.24]) by fmsmga004.fm.intel.com with ESMTP; 21 Dec 2016 07:18:05 -0800 From: Shashank Sharma To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v3 1/3] drm: Create new structure for HDMI info Date: Wed, 21 Dec 2016 20:59:02 +0530 Message-Id: <1482334144-9223-1-git-send-email-shashank.sharma@intel.com> X-Mailer: git-send-email 1.9.1 Cc: Daniel Vetter , Thierry Reding , Jose Abreu X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch creates a new structure drm_hdmi_info (inspired from drm_display_info). Driver will parse HDMI sink's advance capabilities from HF-VSDB and populate this structure. This structure will be kept and used as a sub-class within drm_display_info. We are adding parsing of HF-VSDB In the next patch. V3: Address review comments from Jose - Modify the usage of the structure drm_display_info in other drivers apart from I915 Cc: Thierry Reding Cc: Daniel Vetter Cc: Jose Abreu Suggested-by: Thierry Reding Signed-off-by: Shashank Sharma --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 2 +- drivers/gpu/drm/drm_edid.c | 6 +- drivers/gpu/drm/radeon/radeon_connectors.c | 2 +- include/drm/drm_connector.h | 79 ++++++++++++++++++++++++-- 4 files changed, 79 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 8d1cf2d..270ab5d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -180,7 +180,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { - if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && + if ((connector->display_info.hdmi_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && (mode_clock * 5/4 <= max_tmds_clock)) bpc = 10; else diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 67d6a73..b552197 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -3782,21 +3782,21 @@ static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, if (hdmi[6] & DRM_EDID_HDMI_DC_30) { dc_bpc = 10; - info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; + info->hdmi_info.edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; DRM_DEBUG("%s: HDMI sink does deep color 30.\n", connector->name); } if (hdmi[6] & DRM_EDID_HDMI_DC_36) { dc_bpc = 12; - info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; + info->hdmi_info.edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; DRM_DEBUG("%s: HDMI sink does deep color 36.\n", connector->name); } if (hdmi[6] & DRM_EDID_HDMI_DC_48) { dc_bpc = 16; - info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; + info->hdmi_info.edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; DRM_DEBUG("%s: HDMI sink does deep color 48.\n", connector->name); } diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c index 27affbd..9edd13b 100644 --- a/drivers/gpu/drm/radeon/radeon_connectors.c +++ b/drivers/gpu/drm/radeon/radeon_connectors.c @@ -210,7 +210,7 @@ int radeon_get_monitor_bpc(struct drm_connector *connector) /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { - if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && + if ((connector->display_info.hdmi_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && (mode_clock * 5/4 <= max_tmds_clock)) bpc = 10; else diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index 6e352a0..fba2b88 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -90,6 +90,76 @@ enum subpixel_order { }; /** + * struct drm_hdmi_info - runtime data specific to a connected hdmi sink + * + * Describes a given hdmi display (e.g. CRT or flat panel) and its capabilities. + * Mostly refects the advanced features added in HDMI 2.0 specs and the deep + * color support. This is a sub-segment of struct drm_display_info and should be + * used within. + * + * For sinks which provide an EDID this can be filled out by calling + * drm_add_edid_modes(). + */ + +struct drm_hdmi_info { + + /** + * @edid_hdmi_dc_modes: Mask of supported hdmi deep color modes. Even + * more stuff redundant with @bus_formats. + */ + u8 edid_hdmi_dc_modes; + + /** + * @edid_yuv420_dc_modes: bpc for deep color yuv420 encoding. + * various sinks can support 10/12/16 bit per channel deep + * color encoding. edid_yuv420_dc_modes = 0 means sink doesn't + * support deep color yuv420 encoding. + */ + u8 edid_yuv420_dc_modes; + + +#define DRM_HFVSDB_SCDC_SUPPORT (1<<7) +#define DRM_HFVSDB_SCDC_RR_CAP (1<<6) +#define DRM_HFVSDB_SCRAMBLING (1<<3) +#define DRM_HFVSDB_INDEPENDENT_VIEW (1<<2) +#define DRM_HFVSDB_DUAL_VIEW (1<<1) +#define DRM_HFVSDB_3D_OSD (1<<0) + + /** + * @scdc_supported: Sink supports SCDC functionality. + */ + bool scdc_supported; + + /** + * @scdc_rr_cap: Sink has SCDC read request capability. + */ + bool scdc_rr_cap; + + /** + * @scrambling: Sync supports scrambling for <=340 Mcsc TMDS + * char rates. Above 340 Mcsc rates, scrambling is always reqd. + */ + bool scrambling; + + /** + * @independent_view_3d: Sink supports 3d independent view signaling + * in HF-VSIF. + */ + bool independent_view_3d; + + /** + * @dual_view_3d: Sink supports 3d dual view signaling in HF-VSIF. + */ + bool dual_view_3d; + + /** + * @osd_disparity_3d: Sink supports 3d osd disparity indication + * in HF-VSIF. + */ + bool osd_disparity_3d; +}; + +/** * struct drm_display_info - runtime data about the connected sink * * Describes a given display (e.g. CRT or flat panel) and its limitations. For @@ -179,15 +249,14 @@ struct drm_display_info { bool dvi_dual; /** - * @edid_hdmi_dc_modes: Mask of supported hdmi deep color modes. Even - * more stuff redundant with @bus_formats. + * @cea_rev: CEA revision of the HDMI sink. */ - u8 edid_hdmi_dc_modes; + u8 cea_rev; /** - * @cea_rev: CEA revision of the HDMI sink. + * @ drm_hdmi_info: Capabilities of connected HDMI display */ - u8 cea_rev; + struct drm_hdmi_info hdmi_info; }; int drm_display_info_set_bus_formats(struct drm_display_info *info,