From patchwork Fri Feb 3 09:51:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Abriou X-Patchwork-Id: 9553695 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 25289604A7 for ; Fri, 3 Feb 2017 09:51:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 16DD528462 for ; Fri, 3 Feb 2017 09:51:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0BBAC284E7; Fri, 3 Feb 2017 09:51:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A7DB428462 for ; Fri, 3 Feb 2017 09:51:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7C9956EB3A; Fri, 3 Feb 2017 09:51:37 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id A77AD6EB39 for ; Fri, 3 Feb 2017 09:51:35 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.11/8.16.0.11) with SMTP id v139jl0Q032242; Fri, 3 Feb 2017 10:51:33 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-.pphosted.com with ESMTP id 288ha9ek2w-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 03 Feb 2017 10:51:33 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 181C53A; Fri, 3 Feb 2017 09:51:28 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id F271527A1; Fri, 3 Feb 2017 09:51:27 +0000 (GMT) Received: from localhost (10.201.23.35) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 3 Feb 2017 10:51:27 +0100 From: Vincent Abriou To: Subject: [PATCH 1/3] drm/sti: enable gdp pixel clock in atomic_update Date: Fri, 3 Feb 2017 10:51:22 +0100 Message-ID: <1486115484-13906-2-git-send-email-vincent.abriou@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486115484-13906-1-git-send-email-vincent.abriou@st.com> References: <1486115484-13906-1-git-send-email-vincent.abriou@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.35] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-02-03_08:, , signatures=0 Cc: Yannick Fertre , Vincent Abriou , Fabien Dessenne X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Set gdp pix clock rate and parent in atomic_check function and enable it in the atomic_update only the first time. Signed-off-by: Vincent Abriou --- drivers/gpu/drm/sti/sti_gdp.c | 70 ++++++++++++++++++++----------------------- 1 file changed, 32 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/sti/sti_gdp.c b/drivers/gpu/drm/sti/sti_gdp.c index 877d053..7255234 100644 --- a/drivers/gpu/drm/sti/sti_gdp.c +++ b/drivers/gpu/drm/sti/sti_gdp.c @@ -610,7 +610,6 @@ static int sti_gdp_atomic_check(struct drm_plane *drm_plane, struct sti_plane *plane = to_sti_plane(drm_plane); struct sti_gdp *gdp = to_sti_gdp(plane); struct drm_crtc *crtc = state->crtc; - struct sti_compositor *compo = dev_get_drvdata(gdp->dev); struct drm_framebuffer *fb = state->fb; struct drm_crtc_state *crtc_state; struct sti_mixer *mixer; @@ -648,45 +647,30 @@ static int sti_gdp_atomic_check(struct drm_plane *drm_plane, return -EINVAL; } - if (!gdp->vtg) { - /* Register gdp callback */ - gdp->vtg = compo->vtg[mixer->id]; - if (sti_vtg_register_client(gdp->vtg, - &gdp->vtg_field_nb, crtc)) { - DRM_ERROR("Cannot register VTG notifier\n"); + /* Set gdp clock */ + if (gdp->clk_pix) { + struct clk *clkp; + int rate = mode->clock * 1000; + int res; + + /* + * According to the mixer used, the gdp pixel clock + * should have a different parent clock. + */ + if (mixer->id == STI_MIXER_MAIN) + clkp = gdp->clk_main_parent; + else + clkp = gdp->clk_aux_parent; + + if (clkp) + clk_set_parent(gdp->clk_pix, clkp); + + res = clk_set_rate(gdp->clk_pix, rate); + if (res < 0) { + DRM_ERROR("Cannot set rate (%dHz) for gdp\n", + rate); return -EINVAL; } - - /* Set and enable gdp clock */ - if (gdp->clk_pix) { - struct clk *clkp; - int rate = mode->clock * 1000; - int res; - - /* - * According to the mixer used, the gdp pixel clock - * should have a different parent clock. - */ - if (mixer->id == STI_MIXER_MAIN) - clkp = gdp->clk_main_parent; - else - clkp = gdp->clk_aux_parent; - - if (clkp) - clk_set_parent(gdp->clk_pix, clkp); - - res = clk_set_rate(gdp->clk_pix, rate); - if (res < 0) { - DRM_ERROR("Cannot set rate (%dHz) for gdp\n", - rate); - return -EINVAL; - } - - if (clk_prepare_enable(gdp->clk_pix)) { - DRM_ERROR("Failed to prepare/enable gdp\n"); - return -EINVAL; - } - } } DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n", @@ -724,6 +708,16 @@ static void sti_gdp_atomic_update(struct drm_plane *drm_plane, if (!crtc || !fb) return; + if (!gdp->vtg) { + struct sti_compositor *compo = dev_get_drvdata(gdp->dev); + struct sti_mixer *mixer = to_sti_mixer(crtc); + + /* Register gdp callback */ + gdp->vtg = compo->vtg[mixer->id]; + sti_vtg_register_client(gdp->vtg, &gdp->vtg_field_nb, crtc); + clk_prepare_enable(gdp->clk_pix); + } + mode = &crtc->mode; dst_x = state->crtc_x; dst_y = state->crtc_y;