From patchwork Fri Mar 17 03:54:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Zhong X-Patchwork-Id: 9629733 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C830D60249 for ; Fri, 17 Mar 2017 03:54:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B3E3728653 for ; Fri, 17 Mar 2017 03:54:39 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A6C862867F; Fri, 17 Mar 2017 03:54:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5B9FB28653 for ; Fri, 17 Mar 2017 03:54:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C8E526EC87; Fri, 17 Mar 2017 03:54:38 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pg0-f65.google.com (mail-pg0-f65.google.com [74.125.83.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 217DE6EC87 for ; Fri, 17 Mar 2017 03:54:37 +0000 (UTC) Received: by mail-pg0-f65.google.com with SMTP id g2so8222316pge.2 for ; Thu, 16 Mar 2017 20:54:37 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=FU8suNJ6+QqXEmuFNE1DROrjqR7jFu2BBaDHPObE7qw=; b=nfK2x3OEvB+B03VVOQwOzqU6GCtB65Zwwt+Ub4fL1PJhlxFnmCPFIY574CJfEimHFA XUFKFfvc7uySYxb58E+LoUejkvwK+kET+c/wFNAsxmQ/xg7R/UCWrIVQoK9d8OIlxISj f2JXv1uU5l18VtfrefZ6mIbgybstMLLfFdB+TKu1pce67wEuCcBSeZtwKLxzqFCdUhJy Qc3VFIZG/O+K7iHkwIZkGSk5xrshoicH0QOJha3d4LRAVTxOt6ZO6E9esvLWPktPvKfO l6SEQ4FvUy946Lry42MAZNkvfI0pl9jlkElinub8jdDTt6BKWpKOXjDNOVLJ/vnxKbUq El+w== X-Gm-Message-State: AFeK/H15SHKMjl1MsfdqIjP304pPMUDHwPVUc3P0PRI0ZaWpExIK6HcsYwrZnJ+FgDfpJw== X-Received: by 10.84.232.129 with SMTP id i1mr17045505plk.129.1489722876781; Thu, 16 Mar 2017 20:54:36 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id a77sm13221614pfj.1.2017.03.16.20.54.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 16 Mar 2017 20:54:36 -0700 (PDT) From: Chris Zhong To: linux-rockchip@lists.infradead.org Subject: [PATCH v3 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399 Date: Fri, 17 Mar 2017 11:54:21 +0800 Message-Id: <1489722865-22122-2-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 2.6.3 In-Reply-To: <1489722865-22122-1-git-send-email-zyw@rock-chips.com> References: <1489722865-22122-1-git-send-email-zyw@rock-chips.com> Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Chris Zhong , linux-arm-kernel@lists.infradead.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is disabled, MIPI phy can not work. Let's return a error if there is no phy_cfg_clk in dts property, when the pdata match RK3399. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul --- Changes in v3: - add a DW_MIPI_NEEDS_PHY_CFG_CLK for RK3399 Changes in v2: None drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index f84f9ae..68f48b0 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -251,6 +251,8 @@ #define THS_PRE_PROGRAM_EN BIT(7) #define THS_ZERO_PROGRAM_EN BIT(6) +#define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) + enum { BANDGAP_97_07, BANDGAP_98_05, @@ -279,6 +281,7 @@ struct dw_mipi_dsi_plat_data { u32 grf_switch_reg; u32 grf_dsi0_mode; u32 grf_dsi0_mode_reg; + unsigned int flags; unsigned int max_data_lanes; }; @@ -1136,6 +1139,7 @@ static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = { .grf_switch_reg = RK3399_GRF_SOC_CON19, .grf_dsi0_mode = RK3399_GRF_DSI_MODE, .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22, + .flags = DW_MIPI_NEEDS_PHY_CFG_CLK, .max_data_lanes = 4, }; @@ -1227,15 +1231,13 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, clk_disable_unprepare(dsi->pclk); } - dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); - if (IS_ERR(dsi->phy_cfg_clk)) { - ret = PTR_ERR(dsi->phy_cfg_clk); - if (ret != -ENOENT) { + if (pdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { + dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); + if (IS_ERR(dsi->phy_cfg_clk)) { + ret = PTR_ERR(dsi->phy_cfg_clk); dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret); return ret; } - dsi->phy_cfg_clk = NULL; - dev_dbg(dev, "have not phy_cfg_clk\n"); } ret = clk_prepare_enable(dsi->pllref_clk);