From patchwork Wed Mar 22 01:54:48 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Zhong X-Patchwork-Id: 9637927 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9EEF5602D6 for ; Wed, 22 Mar 2017 01:56:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 913441FE85 for ; Wed, 22 Mar 2017 01:56:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 859842830A; Wed, 22 Mar 2017 01:56:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 37E0F1FE85 for ; Wed, 22 Mar 2017 01:56:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 033816E7CB; Wed, 22 Mar 2017 01:56:49 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pf0-f195.google.com (mail-pf0-f195.google.com [209.85.192.195]) by gabe.freedesktop.org (Postfix) with ESMTPS id 294BB6E7CA for ; Wed, 22 Mar 2017 01:56:48 +0000 (UTC) Received: by mail-pf0-f195.google.com with SMTP id p189so18938718pfp.0 for ; Tue, 21 Mar 2017 18:56:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=1hQ8GVb0nTyQ/4Y4I7iqYTJwguRTCjkcgYVTedQNBu4=; b=JRE8r8KKldEJikSxhP5T8DEIFNelrFFxEYt0xtIaaczfTjY2kOfhGyfrQqXPSsJELM atNx97Pec/YnkDQPwaT4WSv+VWPBJfbWjuXPTJl55LAgIpmhEwWqjZdseZm5KyfuDLYI vT5QyyYmjyvozLb77GvMEY1DA5YPbMKTZ5erKG6ZQ3xcMXrFjpRZwLP7GIW+/5ep1E4R Gz5FcqtxoE4dRoJihTCMPb58UKGk+Xh5PmD8H00VVINSWpyfVN7uE+XreyuoQ6IhinNA F4i1FVs7fktxXRp3VCCW9ndQJ8OVqWD0hHvMrxng7nhRuSYZfxSj/ahViiXpavObY6KD 6ltg== X-Gm-Message-State: AFeK/H0vsD3sc/uxkAR5zdh4T99kqdcjaRlXo4A3wF5hY3ukNXl0IKmNV44ohVRLwA8qag== X-Received: by 10.84.193.129 with SMTP id f1mr21106485pld.63.1490147807809; Tue, 21 Mar 2017 18:56:47 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id t6sm42197794pgo.42.2017.03.21.18.56.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 21 Mar 2017 18:56:47 -0700 (PDT) From: Chris Zhong To: linux-rockchip@lists.infradead.org Subject: [PATCH v4 1/4] drm/rockchip/dsi: check phy_cfg_clk only for RK3399 Date: Wed, 22 Mar 2017 09:54:48 +0800 Message-Id: <1490147691-4489-2-git-send-email-zyw@rock-chips.com> X-Mailer: git-send-email 2.6.3 In-Reply-To: <1490147691-4489-1-git-send-email-zyw@rock-chips.com> References: <1490147691-4489-1-git-send-email-zyw@rock-chips.com> Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Chris Zhong , linux-arm-kernel@lists.infradead.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP For RK3399, the phy_cfg_clk is a required clock, if phy_cfg_clk is disabled, MIPI phy can not work. Let's return a error if there is no phy_cfg_clk in dts property, when the pdata match RK3399. Signed-off-by: Chris Zhong Reviewed-by: Sean Paul --- Changes in v4: None Changes in v3: - add a DW_MIPI_NEEDS_PHY_CFG_CLK for RK3399 Changes in v2: None drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index f84f9ae..68f48b0 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -251,6 +251,8 @@ #define THS_PRE_PROGRAM_EN BIT(7) #define THS_ZERO_PROGRAM_EN BIT(6) +#define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) + enum { BANDGAP_97_07, BANDGAP_98_05, @@ -279,6 +281,7 @@ struct dw_mipi_dsi_plat_data { u32 grf_switch_reg; u32 grf_dsi0_mode; u32 grf_dsi0_mode_reg; + unsigned int flags; unsigned int max_data_lanes; }; @@ -1136,6 +1139,7 @@ static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = { .grf_switch_reg = RK3399_GRF_SOC_CON19, .grf_dsi0_mode = RK3399_GRF_DSI_MODE, .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22, + .flags = DW_MIPI_NEEDS_PHY_CFG_CLK, .max_data_lanes = 4, }; @@ -1227,15 +1231,13 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master, clk_disable_unprepare(dsi->pclk); } - dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); - if (IS_ERR(dsi->phy_cfg_clk)) { - ret = PTR_ERR(dsi->phy_cfg_clk); - if (ret != -ENOENT) { + if (pdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { + dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); + if (IS_ERR(dsi->phy_cfg_clk)) { + ret = PTR_ERR(dsi->phy_cfg_clk); dev_err(dev, "Unable to get phy_cfg_clk: %d\n", ret); return ret; } - dsi->phy_cfg_clk = NULL; - dev_dbg(dev, "have not phy_cfg_clk\n"); } ret = clk_prepare_enable(dsi->pllref_clk);