From patchwork Tue Apr 25 13:19:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christian_K=C3=B6nig?= X-Patchwork-Id: 9698173 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3A228603F6 for ; Tue, 25 Apr 2017 13:20:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 356F82865B for ; Tue, 25 Apr 2017 13:20:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3457928625; Tue, 25 Apr 2017 13:20:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B5E1628625 for ; Tue, 25 Apr 2017 13:20:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AF73D6E3A4; Tue, 25 Apr 2017 13:20:02 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from pegasos-out.vodafone.de (pegasos-out.vodafone.de [80.84.1.38]) by gabe.freedesktop.org (Postfix) with ESMTP id 3FD7B6E3AB for ; Tue, 25 Apr 2017 13:20:01 +0000 (UTC) Received: from localhost (localhost.localdomain [127.0.0.1]) by pegasos-out.vodafone.de (Rohrpostix1 Daemon) with ESMTP id A5F1B261F04; Tue, 25 Apr 2017 15:20:00 +0200 (CEST) X-Virus-Scanned: amavisd-new at vodafone.de Authentication-Results: rohrpostix1.prod.vfnet.de (amavisd-new); dkim=pass header.i=@vodafone.de Received: from pegasos-out.vodafone.de ([127.0.0.1]) by localhost (rohrpostix1.prod.vfnet.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KuJy84io3IaX; Tue, 25 Apr 2017 15:19:58 +0200 (CEST) Received: from smtp-05.vodafone.de (smtp-05.vodafone.de [10.215.254.32]) by pegasos-out.vodafone.de (Rohrpostix1 Daemon) with ESMTP id 471A1261F07; Tue, 25 Apr 2017 15:19:58 +0200 (CEST) X-DKIM: OpenDKIM Filter v2.6.8 pegasos-out.vodafone.de 471A1261F07 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vodafone.de; s=mail; t=1493126398; bh=KAI7zpPdrPCwuOHuNf06SeMkMoKRAv1+oNtFDPJjFUg=; h=From:To:Subject:Date:In-Reply-To:References; b=roim1bPDt5IET7dqnhTh5DqBfY4bW9rZlu0d2txAH0aVnTJeVMTDXqlhBN6AAkc9B /kSHLe0hghLJ5yxqMisS3lP6wmTTmqoXVv7EpnM4bpVN0QoVcSfZxfRj5Wur1TDU5v PAI55CRiVqVR5EQGMcjKdC+HmV3H99JRxx11zGdE= X-Virus-Scanned: amavisd-new at vodafone.de Received: from smtp-05.vodafone.de ([127.0.0.1]) by localhost (xsmail-dmz1.prod.vfnet.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id K5S6EP0PGH0H; Tue, 25 Apr 2017 15:19:57 +0200 (CEST) From: =?UTF-8?q?Christian=20K=C3=B6nig?= To: helgaas@kernel.org, linux-pci@vger.kernel.org, dri-devel@lists.freedesktop.org, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/4] x86/PCI: Enable a 64bit BAR on AMD Family 15h (Models 30h-3fh) Processors v2 Date: Tue, 25 Apr 2017 15:19:53 +0200 Message-Id: <1493126394-1239-4-git-send-email-deathsimple@vodafone.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1493126394-1239-1-git-send-email-deathsimple@vodafone.de> References: <1493126394-1239-1-git-send-email-deathsimple@vodafone.de> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP From: Christian König Most BIOS don't enable this because of compatibility reasons. Manually enable a 64bit BAR of 64GB size so that we have enough room for PCI devices. v2: style cleanups, increase size, add resource name, set correct flags, print message that windows was added Signed-off-by: Christian König Reviewed-by: Alex Deucher --- arch/x86/pci/fixup.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index 6d52b94..8d949c4 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c @@ -571,3 +571,56 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, pci_invalid_bar); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6f60, pci_invalid_bar); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fa0, pci_invalid_bar); DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, pci_invalid_bar); + +static void pci_amd_enable_64bit_bar(struct pci_dev *dev) +{ + uint32_t base, limit, high; + struct resource *res, *conflict; + unsigned i; + + for (i = 0; i < 8; ++i) { + pci_read_config_dword(dev, 0x80 + i * 0x8, &base); + pci_read_config_dword(dev, 0x180 + i * 0x4, &high); + + /* Is this slot free? */ + if ((base & 0x3) == 0x0) + break; + + base >>= 8; + base |= high << 24; + + /* Abort if a slot already configures a 64bit BAR. */ + if (base > 0x10000) + return; + } + if (i == 8) + return; + + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) + return; + + res->name = "PCI Bus 0000:00"; + res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM | + IORESOURCE_MEM_64 | IORESOURCE_WINDOW; + res->start = 0x100000000; + res->end = 0xfd00000000 - 1; + + /* Just grab the free area behind system memory for this */ + while ((conflict = request_resource_conflict(&iomem_resource, res))) + res->start = conflict->end + 1; + + dev_info(&dev->dev, "adding root bus resource %pR\n", res); + + base = ((res->start >> 8) & 0xffffff00) | 0x3; + limit = ((res->end + 1) >> 8) & 0xffffff00; + high = ((res->start >> 40) & 0xff) | + ((((res->end + 1) >> 40) & 0xff) << 16); + + pci_write_config_dword(dev, 0x180 + i * 0x4, high); + pci_write_config_dword(dev, 0x84 + i * 0x8, limit); + pci_write_config_dword(dev, 0x80 + i * 0x8, base); + + pci_bus_add_resource(dev->bus, res, 0); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);