From patchwork Wed May 17 07:56:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 9730331 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 82CDE60138 for ; Wed, 17 May 2017 07:57:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 74A3020009 for ; Wed, 17 May 2017 07:57:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6963828458; Wed, 17 May 2017 07:57:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DD4B820009 for ; Wed, 17 May 2017 07:57:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CE3B36E3C1; Wed, 17 May 2017 07:57:25 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by gabe.freedesktop.org (Postfix) with ESMTPS id 681906E3C1 for ; Wed, 17 May 2017 07:57:25 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v4H7v3p2003777; Wed, 17 May 2017 02:57:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1495007823; bh=YY7B54wRh1TIjWd7SAKO4Arm0N8VJOM7ykElMV6qvtI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Q/S2A2EMmIuegOzs52dr0WiJznSLdNdo99FzdjTB5ReYKjvs8JW9/peBkhoTY7eW+ ++YfTq2USTwKZM8j9iCHUB4IoyvptNFtYXiGnMGtu4X1le9uBoaRCiu+C76+UVkOTb muzuhJtijCYoYmZzq1jQTylHVLlgZSUfsYx63Ac8= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4H7uwIG016049; Wed, 17 May 2017 02:56:58 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Wed, 17 May 2017 02:56:57 -0500 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v4H7ulGX013387; Wed, 17 May 2017 02:56:56 -0500 From: Tomi Valkeinen To: , Laurent Pinchart Subject: [PATCH 6/7] drm/omap: fix YUV422 rotation with TILER Date: Wed, 17 May 2017 10:56:43 +0300 Message-ID: <1495007804-6133-7-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1495007804-6133-1-git-send-email-tomi.valkeinen@ti.com> References: <1495007804-6133-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Cc: Tomi Valkeinen , Jyri Sarha X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP TILER rotation with YUV422 pixelformats does not work at the moment. All other pixel formats work, because the pixelformat's pixel size is equal to tiler unit size (e.g. XR24's pixel size is 32 bits, and the TILER unit size that has to be used is 32 bits). For YUV422 formats this is not the case, as the TILER unit size has to be 32 bits, but the pixel size is 16 bits. The end result is OCP errors and sync losts. This patch adds the code to adjust the variables for YUV422 formats. We could make the code more generic by passing around the pixel format, rotation type, angle and the tiler unit size, which would allow us to do calculations without special case for YUV422. However, this would make the code more complex, and at least for now this is much more easier to handle with these two special cases for YUV422. Signed-off-by: Tomi Valkeinen Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/omapdrm/dss/dispc.c | 20 ++++++++++++++++++-- drivers/gpu/drm/omapdrm/omap_fb.c | 14 ++++++++++++++ 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index a25db6e25165..80c75e5913cb 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -1917,7 +1917,8 @@ static s32 pixinc(int pixels, u8 ps) static void calc_offset(u16 screen_width, u16 width, u32 fourcc, bool fieldmode, unsigned int field_offset, unsigned *offset0, unsigned *offset1, - s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) + s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim, + enum omap_dss_rotation_type rotation_type, u8 rotation) { u8 ps; @@ -1925,6 +1926,20 @@ static void calc_offset(u16 screen_width, u16 width, DSSDBG("scrw %d, width %d\n", screen_width, width); + if (rotation_type == OMAP_DSS_ROT_TILER && + (fourcc == DRM_FORMAT_UYVY || fourcc == DRM_FORMAT_YUYV) && + drm_rotation_90_or_270(rotation)) { + /* + * HACK: ROW_INC needs to be calculated with TILER units. + * We get such 'screen_width' that multiplying it with the + * YUV422 pixel size gives the correct TILER container width. + * However, 'width' is in pixels and multiplying it with YUV422 + * pixel size gives incorrect result. We thus multiply it here + * with 2 to match the 32 bit TILER unit size. + */ + width *= 2; + } + /* * field 0 = even field = bottom field * field 1 = odd field = top field @@ -2473,7 +2488,8 @@ static int dispc_ovl_setup_common(enum omap_plane_id plane, calc_offset(screen_width, frame_width, fourcc, fieldmode, field_offset, &offset0, &offset1, &row_inc, &pix_inc, - x_predecim, y_predecim); + x_predecim, y_predecim, + rotation_type, rotation); DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", offset0, offset1, row_inc, pix_inc); diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c b/drivers/gpu/drm/omapdrm/omap_fb.c index bd05976fc20b..e5cc13799e73 100644 --- a/drivers/gpu/drm/omapdrm/omap_fb.c +++ b/drivers/gpu/drm/omapdrm/omap_fb.c @@ -184,16 +184,30 @@ void omap_framebuffer_update_scanout(struct drm_framebuffer *fb, orient = drm_rotation_to_tiler(state->rotation); + /* + * omap_gem_rotated_paddr() wants the x & y in tiler units. + * Usually tiler unit size is the same as the pixel size, except + * for YUV422 formats, for which the tiler unit size is 32 bits + * and pixel size is 16 bits. + */ + if (fb->format->format == DRM_FORMAT_UYVY || + fb->format->format == DRM_FORMAT_YUYV) { + x /= 2; + w /= 2; + } + /* adjust x,y offset for flip/invert: */ if (orient & MASK_Y_INVERT) y += h - 1; if (orient & MASK_X_INVERT) x += w - 1; + /* Note: x and y are in TILER units, not pixels */ omap_gem_rotated_dma_addr(plane->bo, orient, x, y, &info->paddr); info->rotation_type = OMAP_DSS_ROT_TILER; info->rotation = state->rotation ?: DRM_ROTATE_0; + /* Note: stride in TILER units, not pixels */ info->screen_width = omap_gem_tiled_stride(plane->bo, orient); } else { switch (state->rotation & DRM_ROTATE_MASK) {